Timing, especially in sequential logic, confuses me a lot. I devised an example and drew a timing diagram and I would like to ask some question regarding it; all of them are about the same issue.
Here is the VHDL code I wrote. It does not make sense in terms of functionality, but what I focus on is the timing of it. I have a black box component (no implementation of it, I just made it up and it is only sequential, no combinational part and it only uses the rising edge of the clock in its process part) and in a dummy module I use that module. It takes 2 inputs and when enabled, one clock cycle later it sets the output and pulls high its output valid pin for one cycle.
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity dummy is Port ( clk : in std_logic; dummy_enable : in std_logic; dummy_done : out std_logic ); end dummy; architecture Behavioral of dummy is COMPONENT b_box PORT ( clk : IN STD_LOGIC; enable_b_box : IN STD_LOGIC; input_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); input_2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); output_valid : IN STD_LOGIC; output : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END COMPONENT; signal enable_bb : std_logic := '0'; signal input_1_bb : std_logic_vector(31 downto 0); signal input_2_bb : std_logic_vector(31 downto 0); signal output_valid_bb : std_logic := '0'; signal output_bb : std_logic_vector(31 downto 0); begin bb : b_box PORT MAP ( clk => clk, enable_b_box => enable_bb, input_1 => input_1_bb, input_2 => input_2_bb, output_valid => output_valid_bb, output => output_bb ); process(clk) begin if rising_edge(clk) then if dummy_enable = '1' then enable_bb <= '1'; input_1_bb <= some random number_1; input_2_bb <= some random number_2; else enable_bb <= '0'; end if; if output_valid_bb = '1' then dummy_done <= '1'; else dummy_done <= '0'; end if; end if; end process; end Behavioral;
At t=1, b_box enable goes high, at the same time inputs are provided to it. Is there a risk of metastability for b_box component? Would it be better if b_box enable is kept high for 2 clock cycles as it can miss the enable signal in its process code, I think?
When output valid goes high for one clock cycle, dummy done is pulled high one cycle later. Is there a risk for metastability as well for dummy done because output valid is only high between 2 rising edges (from t=2 to t=3). I believe set up time and hold time problems must occur for dummy done.
I mean one signal goes low at the same time one goes up according to the first signal. This feels wrong because at the clock rising edge when sampled, it could be sampled 1 or 0.