0
\$\begingroup\$

I'm designing a basic PCB for testing equipment in lab. The goal is to take a clock input, a clock enable (from a PC indicating that the measurement is beginning), and then distribute it to a number of additional instruments which are all positive edge sensitive. I would like it to work for clocks of up to 1 MHz. Since the PC signal isn't synchronized to the input clock, I run the risk of generating short pulses if the enable signal arrives while the clock is already high which could corrupt data or measurements.

Instead, I would like to wait one or more cycles and then enable the output while the clock is low so that the next output edge will rise synchronously with the input clock:

timing diagram

Here is my schematic that attempts this:

schematic

Invert clock (SN74LVC1G04DBVR), feed into two sequential D flip-flops (74VHCV574FT), and then use that as the output enable for the clock fan out chip (CDCLVC1108PW). This should store the Enable signal for 1.5 cycles and then pass it through just after the next following clock edge. I used two sequential flip flops in order to reduce the (probably low) likelihood of a metastable state that lasts more than 0.5 microseconds.

Question

Does this design work and is it a sensible approach to avoid producing short clock cycles and spurious rising edges? Is there anything I am doing wrong or not considering?

\$\endgroup\$
1
  • \$\begingroup\$ Sadly all 8 flip flops share a single clock, otherwise you could clock one from the inverted clock and one from the non-inverted clock, which should clear up any skulduggery that might happen if the enable were to change exactly in a clock transition. What you’ve got looks fine, but I’m hesitant to post this as an answer in case I’ve missed anything. BTW 1uF decaps seem rather large, consider replacing some with 100n or 10n. \$\endgroup\$
    – Frog
    Feb 5 at 5:17

1 Answer 1

Reset to default
0
\$\begingroup\$

The n-flip flop synchronizer is a classic and widely used technique. The only catch is that you're not synchronizing to CLK, you're synchronizing to the inverted clock. The inverter adds a small gate delay and jitter to the clock. As long as this delay doesn't cause your synchronized signal to violate the setup time requirement of the enable signal, you're fine (and this should be the case unless your clock is extremely fast, which 1 MHz isn't in this case).

You should be able to simulate this to make sure it does what you expect before trying it in hardware.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.