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I'm very confused about why we need phase-locked loops.

On ScienceDirect.com, it reads:

Phase-locked loops (PLLs) have many applications in the communications world. The main purpose of a PLL circuit is to synchronize an output oscillator signal with a reference signal.

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Why don't we just simply wire ref_input and output_signal like this:

ref_input and output_signal must be perfectly synchronized.

enter image description here

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    \$\begingroup\$ Often PLL's are used in conjunction with frequency multipliers and dividers to not only synchronize frequency, but also to generate additional frequencies. Also, if you refer to your diagram, you will see that the PLL creates FM output. Sometimes the FM output may be needed or desired. In fact, the FM output may be the only thing that is desired in some cases. \$\endgroup\$
    – user57037
    Feb 6, 2022 at 18:24
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    \$\begingroup\$ Suppose your input is a serial data stream without any clock. A PLL can extract and synchronize from this stream to a periodic clock to be used for timing on the receiver (clock recovery). A wire can not do that. \$\endgroup\$
    – pat
    Feb 7, 2022 at 0:49
  • \$\begingroup\$ @pat the data stream has to have some kind of an embedded timing reference to do that. \$\endgroup\$ Feb 7, 2022 at 0:53
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    \$\begingroup\$ @hacktastical. Yes, the in the case I described (and practically, e.g. ethernet) there are data streams that do not have a separate periodic clock, but do have embedded edges in the data that can allow clock extraction, which a PLL provides. A wire will not do that (op question). \$\endgroup\$
    – pat
    Feb 7, 2022 at 0:58
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    \$\begingroup\$ @hacktastical. I meant that a PLL can take as input a signal that is NOT a periodic clock ('data stream without an explicit clock'), but yes, it can have clock and timing information embedded in the data stream (usually edges) and recovered via a PLL. OP asked why can't we just use a wire to synchronize. This example serves as a reason why not. \$\endgroup\$
    – pat
    Feb 7, 2022 at 1:06

6 Answers 6

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PLLs provide a number of features that the direct connection doesn't. A few examples:

  • With proper filtering in the loop filter, they can provide a more stable clock by attenuating jitter

  • When a self clocking signal is used in a communication system, a PLL is used as a building block in the mechanism to recover the reference clock from that signal at the receiver, even when not every clock edge is present.

  • By inserting clock dividers into the input and feedback paths, it's possible to synthesize related clocks that are the input frequency times some factor (e.g. doubling or multiplying by a simple fraction like 5/4). If this divider is adjustable, then you can select different clock frequencies on the fly, while still using a highly precise piezoelectric reference which may itself not be able to operate at the frequency of interest.

    This is especially important when generating fast clocks in the GHz range -- even if adjustment is not required, quartz crystals cannot be reliably and effectively manufactured and operated for GHz range frequencies (although FBARs and AlN contour mode resonators can).

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    \$\begingroup\$ Another benefit of a PLL is that a crystal resonating in the GHz range will fail mechanically. So you can have a very high Q crystal oscillator in the MHz range and a low Q VCO in a PLL such that you can produce high Q oscillation at high frequencies. \$\endgroup\$
    – user110971
    Feb 6, 2022 at 21:04
  • \$\begingroup\$ @user110971 - although then you still have issues with short-to-mid-term jitter, which can be a problem in certain applications. \$\endgroup\$
    – TLW
    Feb 8, 2022 at 5:33
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One of the main uses of a PLL is basically an opamp for clocks, with input/output in frequency instead of voltage. You put a transfer function in the feedback (for example a divider) and you get the opposite transfer function in the output (in this case, gain). Just like an opamp wired for gain. Similar loop stability conditions apply (plus a few more, due to its discrete time nature).

So if you want to run a >100MHz-GHz CPU, you won't use a crystal oscillator at that frequency. That would either be expensive or unobtainium. It is much cheaper to use an oscillator at something like 8-33 Mhz and multiply its frequency with a PLL, especially since these days, the PLL is integrated inside the CPU chip anyway. The multiplication ratio can be integer or fractional, and if the specific PLL allows it, it can also be changed on the fly with the VCO transitioning smoothly from one frequency to the other without generating glitches or short clock periods that would violate the timing requirements of the device that it clocks. A fractional-N PLL can also multiply by a real number, not just a fraction.

The PLL in the question doesn't have a divider in the feedback network, so it won't do frequency multiplication. The other main use is clock recovery and cleanup. Say you have a data transmission with embedded clock, like Ethernet or USB. The clock has to be recovered from the timing of its edges. But when your signal has two identical consecutive bits, there is no edge between them, the signal level stays the same. So, to know when the first bit ends and when the next bit starts, you need a free-running local clock that is synchronized to the data being received. That's what the PLL does in this case, while also cleaning up data-dependent jitter.

Another use of a PLL is phase-shifting a clock. Say you have a clock, and you want a copy of it, but with the edges shifted by a delay "t" that can be positive or negative. A positive delay is not difficult to implement, but a negative delay requires time travel. So instead you use a PLL, synchronize its local oscillator to the incoming clock with a phase shift "period-t" and you get your negative delay.

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    \$\begingroup\$ “a negative delay requires time travel” – well, for a (perfectly) periodic signal, a negative delay t is equivalent to a positive delay Tt. But, there are other reasons to prefer a PLL over literal delay for phase shifting. \$\endgroup\$ Feb 7, 2022 at 20:33
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In the example shown, the PLL is used for FM demodulation. To do this the VCO tracks the incoming Ref input. If the input frequency increases, the voltage to the VCO must increase in order for the VCO freq to match the Ref input freq. If the Ref input freq decreases, the VCO voltage must decrease. This means the VCO voltage represents the modulation.

This is one of the uses for a PLL. The other answers have examples of other uses. It is a very useful building block.

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  • \$\begingroup\$ Alternatively, for PM, make the loop filter bandwidth less than the range of modulating frequencies. Then the VCO tracks the long-term average of the input frequency (i.e., the carrier frequency), and the modulation appears at the phase detector output. \$\endgroup\$
    – Dave Tweed
    Feb 6, 2022 at 16:36
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PLL`s are necessary for receiving and processing signals having very small amplitudes - for example, for communcation with satellites and deep space probes. Because of such small amplitudes - and the unavoidable noise disturbances - it is absolutely necessary to keep the receiving bandwidth as small as possible.

More than that, for further processing we need a clean and noise-"free" signal which

  • is phase-coherent with the received signal,
  • can follow frequency deviations (tracking possibilities)
  • has a very small jitter, and
  • has a constant amplitude.

For this purpose, the best (only?) solution is the PLL technique.

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This is only one of many applications:

Given your PC's Ethernet PHY has a frequency of F-X, where F is the nominal Frequency and X is the deviation, and the other Ethernet PHY (e.g. in your switch) has an internal frequency of F+Y, the problem is that the frequency of the embedded clock in the signals sent by your PC is too low (e.g. instead of 125MHz it's only 124.8MHz). Now when the switch samples the signal with its own frequency, which is slow but also with a different deviation, it is not sampling the bits in the middle (the ideal sampling point). So after some data has been transmitted it will eventually sample even the wrong bit (both of the wrong clocks will superpose) as the sampling position will wander according to the clock deviations.

Here a PLL can solve the problem: the receiver will use a phase detector to reconstruct the embedded clock of the sender and use a PLL to map the sender's clock to the receiver's clock (measure the superposed deviation). So it can estimate where the middle of the bits is and sample the incoming signal correctly (given it has a method to move its sampling point).

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If your circuit is a simple one with undemanding timing, you can indeed use an unmodified clock without a PLL.

When things get trickier, a PLL can solve system timing problems by using its ability to phase-align its feedback to a reference. This allows creating zero-skew copies of a clock, or clocks with modified skew or phase to enhance data setup or hold time in a clocked system.

In other words, PLLs give an additional degree of freedom - well-controlled phase - in making clocks.

Besides this, PLLs can multiply reference clocks to higher frequencies, and they can remove jitter (phase noise) for critical clocks, such as those used for ADCs / DACs and for RF work.

A related circuit - the Delay-Locked Loop, or DLL, is also used for system timing. It’s an essential element of DDRx timing for example.

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