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I'm new to circuit design. I'm trying to design a clock for a circuit containing 8 SPI to CAN devices. However, I'm not sure if it's possible with a single clock (perhaps this reference). As I'm not sure, I'm looking for a clock buffer. However, my SPI to CAN device accepts as VIH 0.85 VDD (which for 5 V it is 4.25 V) and some of the references for clock buffers report two different VOH, for example this one:

enter image description here

which shows an output high voltage of 2.4 V (which won't be useful) and a CMOS level output high voltage of VDD - 0.4 (or 4.4 V) which is good enough.

What is the difference between both voltages? Would this reference output enough voltage on the clock so it fits my SPI to CAN VIH requirements?

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The two specified VOH are when driving different loads (IOH).

At 35 mA load, the output will be at least 2.4 V. At only 12 mA load, the output will be at least Vdd-0.4 V.

So as long as you don't load that output terribly much, it can fulfill the 4.25 V required by the SPI-to-CAN device.
And as long as the only load is 8 CMOS inputs, the load current will be very moderate so it should work fine.

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