# PFC voltage loop bandwidth

I have two questions about PFC control problem.

1.) For PFC application, the current loop bandwidth needs to be high. But I don't understand why voltage loop bandwidth needs to be slow. What's the impact of voltage loop bandwidth is very high.

2.) PFC output voltage includes double line frequency, if we do the feedback control the system will grab the double line voltage, in this situation how to avoid this happening. Because all I want to know is a constant voltage.

• What does this mean precisely current loop bandwidth? Feb 9 at 16:42
• Describing bandwidth as high and slow are not great descriptions, numbers would be better. You may also want to supply a diagram of the PFC controller your describing and how the voltage and current are being measured Feb 9 at 17:54
• @VoltageSpike The system switching frequency is 100kHz the current loop is 10kHz, how to decide the voltage loop bandwidth. >10kHz or <10kHz?
– EEC
Feb 10 at 12:08
• @Andyaka I mean inner loop bandwidth
– EEC
Feb 10 at 12:09
• @EEC I see no loops, or and description of one or two loops, please edit the question Feb 10 at 14:45

At first glance, a PFC (power-factor-correction) and a SMPS (switch-mode power supply or DC-DC converter) may appear very similar. But how they function and their goals are very different:

• The SMPS or DC-DC uses some form of PWM modulation to switch an inductor/transformer, based on the output voltage. So it is regulating the output voltage to some steady level, at the expense of "whatever happens to the input."
• The PFC uses some form of PWM modulation to switch an inductor/transformer, based on linearizing input current. So it is regulating input current to a steady level, while the output can vary. The output voltage is regulated somewhat, but this is a secondary concern.

For PFC application, the current loop bandwidth needs to be high. But I don't understand why voltage loop bandwidth needs to be slow. What's the impact of voltage loop bandwidth [being] very high?

The goal of the PFC is to force current to be drawn from the AC mains at the same time as the voltage. This is the definition of perfect (1.00) power factor, when the drawn current is exactly in time with the mains AC voltage. If the current lags (inductive, is delayed) or leads (capacitive, is early), then the power factor worsens. In most parts of the world, you have to pay for this wasted power.

Figure a) is a typical boost-mode PFC. For the PFC to linearize drawn current, it has to do several things:

• The current loop, very rapidly, compares $$\i_1\$$ against a reference sinusoid multiplied by the output voltage. This (fast) loop ensures that hundreds or thousands of tiny pulses during one AC cycle average out to 0.99 power-factor (current drawn is in-sync with the AC voltage.) This is the primary goal of a PFC.
• However, the instantaneous output voltage cannot be used in the PFC current loop, because the current loop pulses cause the output voltage to change rapidly, and feeding these changes back into the current loop would result in instability and oscillation. So the voltage loop must be "slowed" (by C2, a low-pass filter) to prevent this.

If C2 were reduced (to speed up the voltage loop), erratic behavior would occur, up to oscillation.

PFC output voltage includes double line frequency, if we do the feedback control the system will grab the double line voltage, in this situation how to avoid this happening. Because all I want to know is a constant voltage.

A PFC does not regulate output voltage. It tries to keep it around some value, but PFC output will change with load. Most often, a DC-DC converter (usually a buck type) is added after the PFC like in b) to reduce this voltage and regulate it.

[Ref 1] Fernandez, A. & Sebastián, Javier & Villegas, P. & Hernando, M.M. & Garcia, Jorge. (2003). Dynamic limits of a power factor preregulator. 1697- 1702 vol.4. 10.1109/PESC.2003.1217712. Full paper here.

The current loop pulses cause the output voltage to change rapidly. What does this sentence mean?

Every time the current loop causes the MOSFET to pulse, this results in a pulse through the diode, along $$\i_2\$$. This causes the voltage at the PFC output to pulse also. Since this happens very quickly, we observe the output voltage to be relatively "noisy" and not a smooth DC value.

A PFC does not regulate output voltage. If PFC doesn't regulate output voltage, why need to use voltage loop to control the output voltage?

Because without it, there is no way for the PFC to determine if it should draw more or less power from the mains. The PFC goal is this, in order:

• Draw current matching the voltage by firing only when appropriate to do so.
• Try to keep the output near some defined value.

If there is no load on the PFC, it will happily sit there, pulsing very infrequently, just enough to keep the output voltage near its normal value.

But if a load is added, the average output voltage drops, and this causes the current loop to pulse longer, which draws more power from the mains, which eventually increases the output voltage again.

Now if this load is removed, the average output voltage will rise because the current loop is still pulsing to supply the (now missing) load. The rising output voltage eventually causes the current loop to pulse shorter, which draws less power from the mains, which eventually lets the output voltage decrease.

Such behavior (automatic self-adjustment) is sometimes called a servo circuit. Meaning, a circuit used to provide control of a desired operation through the use of feedback.

A PFC has two servo mechanisms - the current loop, and the voltage loop.

If C2 were reduced (to speed up the voltage loop), erratic behavior would occur, up to oscillation. Erratic behavior is the input current is not a good sine wave?

Erratic behavior is instability of both the (fast) current loop, and the (slow) voltage loop, since they work together. The level of instability depends on the speed of the voltage loop. As the voltage loop speeds up, it introduces more error and noise into the current loop. The current loop tries to compensate by adjusting the drawn current, which then affects the voltage loop. This is an endless cycle, and at some fast voltage loop, neither section will be able to maintain regulation and the whole thing will oscillate, likely destroying itself.

Any instability will manifest as some amount of noise / unregulation / oscillation on the input and output.

• Hi rdtsc, Your explanation is very detailed and clear. Based on your explanation I still have some parts I don't very much understand. 1.) the current loop pulses cause the output voltage to change rapidly. What does this sentence mean? 2.) A PFC does not regulate output voltage. if PFC doesn't regulate output voltage, why need to use voltage loop to control the output voltage? 3.) If C2 were reduced (to speed up the voltage loop), erratic behavior would occur, up to oscillation. erratic behavior is the input current is not a good sine wave?
– EEC
Feb 10 at 15:18