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Here's the current design for Super OSD Lite, an open hardware project to bring a low cost on screen display to the masses. The price target is $71 to $90.

alt text

bigger image

There are components on the bottom, but most components are on the top.

It's one of my first PCB designs involving such a complex circuit, so I expect I've made a few mistakes. Constructive criticism appreciated!

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    \$\begingroup\$ Do you have gerbers or can't you release them? PNG is not the best medium for this :P \$\endgroup\$ – Nick T Nov 2 '10 at 21:48
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    \$\begingroup\$ Open H/W: Gerbers are here: code.google.com/p/super-osd/source/browse/#hg/hardware/… \$\endgroup\$ – Thomas O Nov 2 '10 at 21:49
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    \$\begingroup\$ What are your design rules? Does it pass DRC? That via under D1 looks mighty close to the pads in the PNG image. \$\endgroup\$ – markrages Nov 2 '10 at 23:55
  • \$\begingroup\$ I haven't set up DRC, because I haven't decided on my PCB fab. It fails DRC because it is set up with worst case rules. \$\endgroup\$ – Thomas O Nov 2 '10 at 23:58
  • \$\begingroup\$ +1 for the drawing of the screw with dimensions in silk screen. \$\endgroup\$ – Nick Alexeev Mar 26 '12 at 5:35
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Looks great!

A few thoughts:

  1. Make all your designators readable from one direction (or at least within 90 degrees of each other).

  2. Where you have space, label the pins on your connectors.

  3. Add a pair of vias to ground that you can solder a little loop of wire to. Then you can clip your scope ground to it.

  4. Make sure your CONN2 and CONN3 connector bodies don't overlap in the real world.

  5. The orientation dot for U6 is almost hidden by a via.

  6. Add vias so you can easily probe your EEPROM data lines.

  7. Make sure your mounting holes are sensibly spaced (not 2.718282 inches apart).

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  • \$\begingroup\$ Is 2.718282 a joke, as it happens to be e? \$\endgroup\$ – Thomas O Nov 2 '10 at 22:15
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    \$\begingroup\$ Good idea on the vias for my scope probe. And for the vias for the EEPROM, though the EEPROM shares the same I2C bus as is broken out on CONN6. \$\endgroup\$ – Thomas O Nov 2 '10 at 22:16
  • \$\begingroup\$ I don't have space to fit some designators in the same direction, I know this will lead to me craning my neck but it's to save space and I only intend them to be used for repairs or rework. \$\endgroup\$ – Thomas O Nov 2 '10 at 22:17
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    \$\begingroup\$ @Thomas O: It might have been a joke, yes. But it's actually just an approximation of e-- I didn't have time to write e in full. \$\endgroup\$ – pingswept Nov 2 '10 at 23:16
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    \$\begingroup\$ With a 4x40 hole size, drills, hex keys, and screws/washers/nuts will be in your users' toolboxes and local hardware stores. You can go to 2x56 (#41/.0960") if you really want to, but that makes sourcing much more difficult. \$\endgroup\$ – Kevin Vermeer Nov 3 '10 at 19:59
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Put a part number and revision number on the silkscreen.

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  • \$\begingroup\$ Good idea. I used to have a space for this but I omitted it. \$\endgroup\$ – Thomas O Nov 3 '10 at 17:55
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    \$\begingroup\$ "This space intentionally left blank" could be filled with this info. \$\endgroup\$ – Robert Nov 3 '10 at 18:34
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I checked out the .pcb file from the git repository.

http://super-osd.googlecode.com/hg/hardware/V3%20Lite/pcb-v3-lite.pcb

I loaded it into pcb and ran DRC on it, with the following results:

Rules are minspace 10.01, minoverlap 10.0 minwidth 10.00, minsilk 10.00
min drill 15.00, min annular ring 10.00
Found 251 design rule errors.

Some traces are too close. For example, the via under D1 is 2.5 mils away from shorting out against the pad. It will be very hard for you to find a fab with 2.5 mil spacing capability, and will be extremely expensive if you do.

If you want to have a board that can be manufactured easily, I suggest you adjust the sizes and move traces until DRC passes. Dave of EEVblog fame wrote a good pcb design guide: http://www.alternatezone.com/electronics/files/PCBDesignTutorialRevA.pdf

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  • \$\begingroup\$ It's actually mercurial. Thanks for your DRC run. Are there any other alerts I need to be aware of? \$\endgroup\$ – Thomas O Nov 3 '10 at 0:24
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    \$\begingroup\$ Try setting min space to 8.0 and min width to 8.0 (file->preferences->sizes) and run DRC again. You can go down to about 5/5, but you will pay for it. Also in my experience, you will want to pay for electrical testing when you are pushing the fab's capabilities, which pushes up costs some more. Keep tweaking the design and running the DRC (Connects->Design Rule Checker) until DRC shows no more design errors. The submit the design to freedfm.com for a second opinion and fab quote. Then pour yourself a beer. \$\endgroup\$ – markrages Nov 3 '10 at 0:32
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    \$\begingroup\$ freedfm is great, even if you aren't going to have them fab your board. \$\endgroup\$ – ajs410 Nov 3 '10 at 15:28
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Make a prettier png! Use my "pcbrender" script. pcbrender input.pcb output.png

#/bin/sh

INFILE=$1
OUTFILE=$2

DPI=300
OVERSAMPLE=3

PCB=pcb #/home/markrages/src/pcb/src/pcb

PCBOPTS="-x png --photo-mode --dpi $(( $OVERSAMPLE*$DPI )) --use-alpha --only-visible"

$PCB $PCBOPTS --outfile /tmp/$INFILE.front.png $INFILE && \
$PCB $PCBOPTS --outfile /tmp/$INFILE.back.png --photo-flip-x --photo-flip-y $INFILE && \
montage /tmp/$INFILE.front.png /tmp/$INFILE.back.png -tile x1 -shadow -geometry "+50+50" -resize $(( 100 / $OVERSAMPLE))% -background lightblue $OUTFILE 

rm -f /tmp/$INFILE.front.png /tmp/$INFILE.back.png

Here's the output: alt text

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  • \$\begingroup\$ Thanks for the link! (There is only one GND plane, I am not sure why PCB has put an edge on the image.) \$\endgroup\$ – Thomas O Nov 3 '10 at 0:15
  • \$\begingroup\$ You're right, it's a pcb rendering artifact. I've removed my comment. \$\endgroup\$ – markrages Nov 3 '10 at 0:18
  • \$\begingroup\$ Care to upload high-res versions of those images? I don't have PCB on the machine I'm using right now, and I suspect that many readers don't have it at all. \$\endgroup\$ – Kevin Vermeer Nov 3 '10 at 19:56
  • \$\begingroup\$ The image link is i.imgur.com/pw6xm.jpg . Open it directly and you'll get a bigger size. \$\endgroup\$ – markrages Nov 3 '10 at 20:02
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I don't know what PCB houses require for board production. But stencil printer and pick-and place lines always need 3-4 fiducials on corners of panel. Panel can contain single pattern of board or multiples of patterns if you will go with mass production. The distance from panel edge to center of fiducial is 5-7.5mm. Fiducial is a copper circle 1-1.5 mm diameter. It is surrounded by circle 3-4mm large of bare substrate, so no solder mask is covering fiducial.

Same fiducials should be created on stencil (solder paste mask made of steel)

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First, I see a couple of components (C22, Z6) suspiciously close to the board edge.

For low cost, volume assembly you will want to pick-n-place the parts onto the boards while they are still panelized. Then the individual boards will be cut out of the panel with a pizza-cutter-like tool. This can cause local stress on parts near the board edge and end up damaging them. Ceramic capacitors are particularly susceptible to this type of damage.

Alternative singulation methods are available, but my understanding is that the "pizza cutter" is the lowest cost.

Second, I suspect that your parts placement is generally too tight to get the best pricing for pick&place. Generally I expect to see the spacing between two-terminal passives (0603 or 0805 packages, for example) nearly equal to the size of the components themselves. The spacing between U2 and RTC and CONN7 in particular looks problematic for pick & place and for re-work. The body of other components should be outside the bounding box of the U2 pads to be able to get a soldering iron fixture down onto all the U2 pads at once for rework.

Third, depending on how the assembly will be done, pay special attention to the SMT parts on the backside of the board. For the lowest cost, you might want to keep all SMT off the backside of the board, even if it means making the board a little bit bigger. If you do need to put SMT on the bottom side, keep all SMT parts well away (like 1/4" or more) from all through hole pads. This will enable a selective wave process to attach the through-hole parts and avoid the need for gluing the SMT parts down for wave processing.

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  • \$\begingroup\$ Obviously, all of these issues are moot if you are designing this to be hand-assembled in onesy-twosy quantities. \$\endgroup\$ – The Photon Dec 11 '11 at 2:57
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I am also inexperienced and a learner on this. However, here are my thoughts:

  • I would re-layout the "Buck Power Supply" part. I am hopeful that you can lessen its EMI radiation by reading a little on SMPS PCB design and current loops etc. Especially, see the application notes and sources below that were really helpful to me.
  • For the "Buck Power Supply" part again, the tracks could be wider, I think you have space for that, for example the connection from D2 to L1.
  • Your designators could face the same direction so that one can easily read them without turning his/her head.

Here are some of the sources I remember and benefited much from:

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R6 is damn close to the QFP packaged IC. I would move it away slightly for easy hand-assembly. Also - U4 (your crystal), is your through hole crystal really that small?

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  • \$\begingroup\$ U4 is a HC-49 crystal. \$\endgroup\$ – Thomas O Nov 3 '10 at 13:05
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On the bottom, north of R36, is a GND fill that is isolated from the main GND fill. It looks like this is CONN6-4.

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