Have a look at my PCB design and tell me how I can improve

Question

Here's the current design for Super OSD Lite, an open hardware project to bring a low cost on screen display to the masses. The price target is $71 to $90.

bigger image

There are components on the bottom, but most components are on the top.

It's one of my first PCB designs involving such a complex circuit, so I expect I've made a few mistakes. Constructive criticism appreciated!

Answer 1

Looks great!

A few thoughts:

1. Make all your designators readable from one direction (or at least within 90 degrees of each other).

2. Where you have space, label the pins on your connectors.

3. Add a pair of vias to ground that you can solder a little loop of wire to. Then you can clip your scope ground to it.

4. Make sure your CONN2 and CONN3 connector bodies don't overlap in the real world.

5. The orientation dot for U6 is almost hidden by a via.

6. Add vias so you can easily probe your EEPROM data lines.

7. Make sure your mounting holes are sensibly spaced (not 2.718282 inches apart).

Answer 2

Put a part number and revision number on the silkscreen.

Answer 3

I checked out the .pcb file from the git repository.

http://super-osd.googlecode.com/hg/hardware/V3%20Lite/pcb-v3-lite.pcb

I loaded it into pcb and ran DRC on it, with the following results:

Rules are minspace 10.01, minoverlap 10.0 minwidth 10.00, minsilk 10.00
min drill 15.00, min annular ring 10.00
Found 251 design rule errors.

Some traces are too close. For example, the via under D1 is 2.5 mils away from shorting out against the pad. It will be very hard for you to find a fab with 2.5 mil spacing capability, and will be extremely expensive if you do.

If you want to have a board that can be manufactured easily, I suggest you adjust the sizes and move traces until DRC passes. Dave of EEVblog fame wrote a good pcb design guide: http://www.alternatezone.com/electronics/files/PCBDesignTutorialRevA.pdf

Answer 4

Make a prettier png! Use my "pcbrender" script. pcbrender input.pcb output.png

#/bin/sh

INFILE=$1
OUTFILE=$2

DPI=300
OVERSAMPLE=3

PCB=pcb #/home/markrages/src/pcb/src/pcb

PCBOPTS="-x png --photo-mode --dpi $(( $OVERSAMPLE*$DPI )) --use-alpha --only-visible"

$PCB $PCBOPTS --outfile /tmp/$INFILE.front.png $INFILE && \
$PCB $PCBOPTS --outfile /tmp/$INFILE.back.png --photo-flip-x --photo-flip-y $INFILE && \
montage /tmp/$INFILE.front.png /tmp/$INFILE.back.png -tile x1 -shadow -geometry "+50+50" -resize $(( 100 / $OVERSAMPLE))% -background lightblue $OUTFILE 

rm -f /tmp/$INFILE.front.png /tmp/$INFILE.back.png

Here's the output:

Answer 5

I don't know what PCB houses require for board production. But stencil printer and pick-and place lines always need 3-4 fiducials on corners of panel. Panel can contain single pattern of board or multiples of patterns if you will go with mass production. The distance from panel edge to center of fiducial is 5-7.5mm. Fiducial is a copper circle 1-1.5 mm diameter. It is surrounded by circle 3-4mm large of bare substrate, so no solder mask is covering fiducial.

Same fiducials should be created on stencil (solder paste mask made of steel)

Answer 6

First, I see a couple of components (C22, Z6) suspiciously close to the board edge.

For low cost, volume assembly you will want to pick-n-place the parts onto the boards while they are still panelized. Then the individual boards will be cut out of the panel with a pizza-cutter-like tool. This can cause local stress on parts near the board edge and end up damaging them. Ceramic capacitors are particularly susceptible to this type of damage.

Alternative singulation methods are available, but my understanding is that the "pizza cutter" is the lowest cost.

Second, I suspect that your parts placement is generally too tight to get the best pricing for pick&place. Generally I expect to see the spacing between two-terminal passives (0603 or 0805 packages, for example) nearly equal to the size of the components themselves. The spacing between U2 and RTC and CONN7 in particular looks problematic for pick & place and for re-work. The body of other components should be outside the bounding box of the U2 pads to be able to get a soldering iron fixture down onto all the U2 pads at once for rework.

Third, depending on how the assembly will be done, pay special attention to the SMT parts on the backside of the board. For the lowest cost, you might want to keep all SMT off the backside of the board, even if it means making the board a little bit bigger. If you do need to put SMT on the bottom side, keep all SMT parts well away (like 1/4" or more) from all through hole pads. This will enable a selective wave process to attach the through-hole parts and avoid the need for gluing the SMT parts down for wave processing.

Answer 7

I am also inexperienced and a learner on this. However, here are my thoughts:

• I would re-layout the "Buck Power Supply" part. I am hopeful that you can lessen its EMI radiation by reading a little on SMPS PCB design and current loops etc. Especially, see the application notes and sources below that were really helpful to me.
• For the "Buck Power Supply" part again, the tracks could be wider, I think you have space for that, for example the connection from D2 to L1.
• Your designators could face the same direction so that one can easily read them without turning his/her head.

Here are some of the sources I remember and benefited much from:

• National Semiconductor - Application Note 1229
• Maxim - TUTORIAL 2997
• Analog Devices - An article from Analog Dialogue
• EDN designfeature article by Jay Scolio

Answer 8

R6 is damn close to the QFP packaged IC. I would move it away slightly for easy hand-assembly. Also - U4 (your crystal), is your through hole crystal really that small?

Answer 9

On the bottom, north of R36, is a GND fill that is isolated from the main GND fill. It looks like this is CONN6-4.