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I am routing a SPI line to multiple follower devices.

Currently I have a split in the trace like this:

enter image description here

but it seems like this might not work well.

Are there any best practices for routing to multiple SPI devices in parallel?

\$f\$ = 1MHz
Rise time = 8ns

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  • \$\begingroup\$ What frequency is this? It almost certainly makes zero difference, see more here electronics.stackexchange.com/questions/76406/… \$\endgroup\$
    – BeB00
    Feb 9, 2022 at 18:56
  • \$\begingroup\$ @BeB00 It will be running at max 1MHz with a minimum rise time of 8ns. \$\endgroup\$
    – brunerm99
    Feb 9, 2022 at 19:06
  • \$\begingroup\$ How long is the bus? If 8ns rise time is slow or fast for your bus depends on the bus length. \$\endgroup\$
    – Justme
    Feb 9, 2022 at 21:17
  • \$\begingroup\$ @Justme The longest trace is a ~95mm, so for my material (\$\varepsilon_r=4\$) it should have a propagation time around 0.6ns. I think this should be sufficiently small relative to the 8ns rise time. \$\endgroup\$
    – brunerm99
    Feb 9, 2022 at 22:51

4 Answers 4

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If you have a high frequency SPI clock (>Mhz) with high rise and fall times, you should keep the tracks about the same length and continuous, no "forking" and impedance against ground fairly constant (continous ground underneath and same distance to copper in same layer).

The fork design in your picture induces an "acid trap" in the sharp inner corner, which might cause excessive removal of copper. Not a problem in practice with tracks wider than ~0.15 mm, which is an usual standard design rule for many low cost fabs.

In practice it's unlikely you will experience any difference. It will make more sense to not waste design effort and PCB space to optimise the SPI bus for no reason.

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  • \$\begingroup\$ It seems like forking would be best, since that keeps the length between all the devices more equal? (not that it likely makes any difference in reality). \$\endgroup\$
    – BeB00
    Feb 9, 2022 at 19:00
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    \$\begingroup\$ In practice it's better to take the shortest route to devices and ignore length differences, because then you don't waste PCB space. Only with high frequencies you need to concider shapes of the tracks or forking etc. SPI can be used for high throughput, so there are cases where it does matter. \$\endgroup\$
    – Ralph
    Feb 9, 2022 at 19:06
  • \$\begingroup\$ @BeB00 This is a relatively low speed application (f=1MHz, min rise time=8ns), so I am not too worried about distance differences. \$\endgroup\$
    – brunerm99
    Feb 9, 2022 at 19:14
  • \$\begingroup\$ @Ralph The traces are 10mil (0.25mm). Thanks for the reply, I had never heard of an "acid trap", but glad to hear it shouldn't be an issue. \$\endgroup\$
    – brunerm99
    Feb 9, 2022 at 19:16
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I am wondering if there are any best practices for routing to multiple SPI devices in parallel.

It really depends on the speeds you want to achieve with that SPI bus, anything under 10MHz and you are unlikely to have problems. After ~30MHz capacitance will start to eat into your risetimes, so any way to keep the capacitance low will be your friend.

Another thing that will cause risetimes to become longer is inductance. Usually the biggest source of inductance with PCB routing will come from vias. (A 10mil via will have about 1.2nH of inductance, smaller vias have more inductance)

Traces that are closer to a continuous ground plane will also have lower inductance, consider inductance calculations at 1MHz for PCB traces:

  • 12mil trace adjacent to a continuous ground layer (top two layers in standard 4 layer stackup) will have 8.6nH/in

  • 12mil trace adjacent to a continuous ground layer on bottom of prepeg from continuous ground plane (middle two layers in standard 4 layer stackup) will have 15.3nH/in

  • 8mil trace adjacent to a continuous ground layer (top two layers in standard 4 layer stackup) will have 10.2nH/in

This will make a difference in very long traces (or if you need fast signals)

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It really depends on the length of the traces and the speed of the clock and the rise time of your signal. If the speed is low enough (sub 1Mhz), it won't make much of a difference, and if there is some weird interaction, you can put some series termination on the clock line to reduce it.

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I assume your image is referring to MISO/MOSI lines, because the CS line must be individual for each component without any branching.

Anyway, you can absolutely route traces like you did in the image and it will work just fine. The only complaint one might have is that it doesn't look good because you have a less than 90° angle between two adiacent traces, that's why people often use right angle intersections or multiple 45° intersections: enter image description here

Regarding the distance between the traces instead, usually you don't want to route parallel traces too close to themselves to avoid crosstalk, so you either space them a bit or put a ground trace between them, this won't probably be a problem with SPI lines though given that it's not an high speed protocol like HDMI or USB 3.0.

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    \$\begingroup\$ Sharp inner corners are not adviced for manufacturability though. And USB and HDMI data pairs are instructed to be routed close to each other with a specified impedance. So those advice are not correct. I do agree with style guide, I do that too and if I see a sharp corner I've been autorouting or made some other mistake :) \$\endgroup\$
    – Ralph
    Feb 9, 2022 at 19:12
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    \$\begingroup\$ @Ralph -- acid traps are generally not a problem with today's manufacturing techniques, other than maybe for home-etched boards. \$\endgroup\$ Feb 9, 2022 at 20:10

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