First, please excuse my limited knowledge of electronics and signalling; I'm a programmer, not an engineer.

I am working on building a Game Boy cartridge, and I was hoping to use some AT27LV520 that I have due to having a low profile (Datasheet here).

The Game Boy's cartridge port exposes the entire address bus, the data bus, and a 1MHz clock. Other pins (/CS, /RD, /WR) are only relevant for accessing cartridge RAM. Accessing cartridge ROM is any access when A15 is low. Based on timings here, once A15 is low, the address bus is set, and data must be presented on D0-D7 by the time CLK goes low, which is about 350 ns. Simple enough.

But wait! The Atmel ROMs I have multiplexes the data and address pins. So, the address must be presented, then deasserted so the ROM can assert data on those pins. This can be done with a latch (like a 74LS373) put on the address pins, then assert /OE, no latching necessary. Even that seems excessive; some 74 series part that is basically 8 transistors would do the job.

But what about ALE and /OE? Because the bus as presented isn't multiplexed, no ALE or /OE is generated. I would have to generate them myself. It seems simple: Once A15 goes low, then bring ALE high for 70 ns, wait 12 ns, float the lower 8 address pins (bring the latch's /OE low), wait 13 ns, then pull /OE low until the clock falls. There's enough time to do all of that (at least on paper), but I don't know how to generate those signals with timings like that outside of using a microcontroller, which seems excessive for this task; there's no logic, just blaring signals once one input falls.

More generally, I can't be the first one to want to place a multiplexed memory onto a non multiplexed bus, so it seems there should be a part out there that would take care of this for me. What can I do?

  • \$\begingroup\$ The accepted answer answers the question as asked, but the other given answer provides valuable input and options to the problem as a whole. \$\endgroup\$
    – Orion
    Feb 16, 2022 at 1:27

2 Answers 2


Q1: "I was hoping to use some AT27LV520 that I have due to having a low profile..." and following text.

It's not an X-Y question, so answering the question as asked, rather than suggesting alternative designs it doesn't ask for...

It certainly can be done but the correct part is a small low-cost single-chip FPGA, not an MCU. That's the part for this logic circuit and gives you complete flexibility on pin timing and function.

The cartridge port provides a reset and a 1 MHz bus clock. The FPGA's internal PLL can derive a high frequency logic clock from the 1 MHz. Producing 100 MHz or 200 MHz or even 400 MHz will let you operate the pin functions in 10 ns or 5 ns steps or even 2.5 ns. This is practical considering the simple logic you'll have, though 200 MHz max. will do everything you need.

Low-cost CPLDs/FPGAs don't have 5 V-tolerant inputs. It would need bus level shifters to receive and to drive 5 V GameBoy signals. (This would be true for an MCU, too.) You'd want to drive the data bus strongly to 5 V, not just pass it through a voltage translator which can pull down but not drive high.

FPGA pins needed for the GameBoy cartridge port are:

  • CLK, /RST, A[7:0], /RD, /CS = 12

FPGA pins needed for the FEPROM are:

  • AD[7:0], ALE, /OE = 10

FPGA pins needed for other logic are:

  • Data bus read transceiver: /DOE = 1

Total is 23 I/O pins.

Here are some available example parts you can use. This emphasises small parts but there's many others:

  • Efinix T4F49C2 (£1.90): internal FEPROM, 400 MHz PLL, 33 I/O, 49-pin 3x3 mm, core uses linear Vreg 1.1 V 20 mA
  • Lattice LCMXO3L-4300E-5UWG81CTR1K (£3.50): internal FEPROM, 400 MHz PLLx2, 63 I/O, 81-pin 3.8x3.7 mm, core uses linear Vreg 1.2 V 20 mA
  • Lattice ICE40LP1K-CM36A (guide £2.50): OTP or external SPI FEPROM, 275 MHz PLL, 25 I/O, 36-pin 2.5x2.5 mm, core uses linear Vreg 1.2 V 3 mA

Other parts can have your FEPROM inside them but that is not designing what you've asked. You'd then just use a parallel FEPROM.

The HDL firmware you need is simple enough, with nearly all development/simulation software free. The GameBoy bus transfers need to use the 1 MHz CLK, not just /RD (or /WR) as consecutive reads will hold /RD LOW and modify the address. So CLK is used to identify the individual reads and generate ALE at the right time. The FPGA can do this easily, while an MCU would work hard to keep up.

So the example circuit looks something like this...


simulate this circuit – Schematic created using CircuitLab

It has to be said that the physical bulk of this circuitry would surely negate the space savings of your FEPROM of choice. It would then just be smaller overall to use a parallel FEPROM. Here, it's using a small FPGA plus a small Vreg, as you'd need the voltage translators anyway.

Q2: "I can't be the first one to want to place a multiplexed memory onto a non-multiplexed bus, so it seems there should be a part out there..."

It's a relatively rare requirement amongst all the processing systems out there. Parallel FEPROM is itself a very small percentage of those systems, which are by volume dominated by MCUs with internal FEPROM. When it's needed, it's a bespoke design.

  • \$\begingroup\$ I've generally had a hard time finding parts that have a low enough height to fit in the cart space. These were the only ones I had on hand. Everything seems to be 4mm tall or out of production. Honestly, I'd love a parallel ROM. \$\endgroup\$
    – Orion
    Feb 10, 2022 at 20:12
  • \$\begingroup\$ I wouldn’t dismiss using a microcontroller. I grafted a imxrt1062 onto the bus of a 80’s computer. Servicing the bus took around 60% of a 600MHz cpu but I could emulate just about anything I wanted, with the larger bga package you can route the pcb on 4 layers without much trouble. The solution would consist of a handful of level translators, the micro and a serial flash. The micro has a megabyte of ram and the serial flash could have 16MB, so that should cover the storage issues. \$\endgroup\$
    – Kartman
    Feb 10, 2022 at 22:55
  • \$\begingroup\$ @Kartman, it's the wrong tool for this job. MCUs get pitched for logic substitute jobs so often on this site and it's not suitable part selection, not always. In the same breath, people will consider using an op-amp as a comparator to be sacrilege :-) . The MCU isn't the first choice for a logic job - the CPLD is. MCU's not dismissed, just bettered. I'm agnostic, I have no favourite technologies, I can use either and all and have many times, including what you describe. Part selection is a combination of so many factors, I've found almost always commercial/cost top with technical much lower. \$\endgroup\$
    – TonyM
    Feb 10, 2022 at 23:28
  • \$\begingroup\$ @Orion, it's a fun project :-) I did what you're doing and what Kartman describes, I hung bulk memory and CPU onto an 80's computer using a cheap single-chip FPGA and a QSPI FEPROM. Two chips, one tiny. \$\endgroup\$
    – TonyM
    Feb 10, 2022 at 23:34
  • \$\begingroup\$ @TonyM - i understand where you’re coming from. Using a micro - especially a 600MHz one to do a memory interface is a bit of a sledgehammer solution. When you have 15ns interrupt response times and instruction times in the single digit ns range, thats in the order of TTL prop delays using such a micro starts to make sense. Couple that with a slab of sram on chip the solution starts to look competitive. The micro costs around $10 in small quan vs 5V flash or sram which is getting harder to find and more expensive. Then there’s the cost of 5V cplds. You get USB, sdcard for free. \$\endgroup\$
    – Kartman
    Feb 11, 2022 at 1:03

Maybe you can do it using a parallel EPROM in the thinnest package you can find and then shave off some thickness by placing the chip in a cutout in the PCB.

This technique is illustrated in this image:

enter image description here

(this is the source of the image: https://www.mortoffgames.com/sega-gamegear/games149?product_id=958).

That specific PCB is meant for a normal DIP package, as shown in this video: https://youtu.be/CZGHeoj_COQ, however the important thing is that you use a package with protruding pins.


OTOH, a search on DigiKey shows that many parallel EEPROMs that are also actively manufactured are quite expensive or out of stock.

With the plethora of cheap MCUs out there I wouldn't rule out to use an MCU instead of an EEPROM. I mean, not just as an interface to your multiplexed EPROMS, but to act as the EEPROM.

Any MCU with enough flash and high enough clock can emulate a parallel EEPROM if you know how to program its GPIO ports and you know the timing requirements of the EEPROM to be emulated.

Flash memory in MCUs is particularly cheap compared with external parallel (E)EPROMs of comparable size.


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