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I am interested to write Verilog module which simultaneously will update several outputs Something like following code, makes 3 operations at the same time (clk 10):

module mymodule (a,b,c,d,e);
input a;
input b;
output c;
output d;
output e;

wire b;
wire a;
wire c;
wire d;

reg e;

initial begin
c <=  #10  (a+b);
d <=  #10  a;
e  <= #10  b;
end

endmodule

Is that code legal?

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  • \$\begingroup\$ what is the difference between using assign statements and just giving "=" ? \$\endgroup\$
    – twinkle
    Commented Mar 13, 2013 at 16:19
  • \$\begingroup\$ This was cross posted on StackOverflow. OP wanted the assignment to happen after 10 (ten) timesteps. \$\endgroup\$ Commented Mar 13, 2013 at 19:47

2 Answers 2

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//Not synthesizable because of #delays can not be translated to something that is mapping wires.

reg clk ; //Rising edge every 10 timesteps
initial begin
  clk = 0;
  #5;
  forever begin
    #5 ;
    clk = ~clk;
  end
end

//Synthesizable because I have avoided use of a delay

reg [31:0] counter;
always @(posedge clk or negedge rst_n) begin
  if (~rst_n) begin
    counter <= 32'b0; // <-- reset value! assigned on negedge of reset
  else
    counter <= counter + 1;


always @(posedge clk or negedge rst_n) begin
  if (~rst_n) begin
    c <= 1'b0;
    d <= 1'b0;
    e <= 1'b0;
  end
  else if (counter == 10) begin
    c <=  (a+b);
    d <=   a;
    e <=   b;
    end
  end
endmodule
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  • \$\begingroup\$ It would be helpful to OP to show how a, b, c, d, e are declared. \$\endgroup\$
    – The Photon
    Commented Mar 13, 2013 at 15:47
  • \$\begingroup\$ @zhaba please give a bit more explanation and try to write an answer in such a way that it does not look like yelling. \$\endgroup\$
    – Kortuk
    Commented Mar 13, 2013 at 16:01
  • \$\begingroup\$ @Zhaba we either write very similar code or this is a cleaned up version of my answer from StackoverFlow \$\endgroup\$ Commented Mar 13, 2013 at 19:52
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No. c, d, and e should all be declared as regs

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  • \$\begingroup\$ will the assignment for c and d and e be done at clk = 10? \$\endgroup\$
    – YAKOVM
    Commented Mar 13, 2013 at 10:19
  • \$\begingroup\$ why should they be regs?I have additional module (nextmodule),which gets its input from wire c,if I declare c as reg - how will I transfer the input to nextmodule from c? \$\endgroup\$
    – YAKOVM
    Commented Mar 13, 2013 at 10:20
  • 1
    \$\begingroup\$ You can take the value of a "reg" in exactly the same way as a wire. However, you have another bug: 'initial' means 'do this once at the start of the program'. #10 also means 'with a delay of 10 time units' not at clock pulse 10, and you don't have a clock anyway. \$\endgroup\$
    – pjc50
    Commented Mar 13, 2013 at 13:25
  • \$\begingroup\$ @pjc50: Was about to mention that. Don't confuse time units with clocks. \$\endgroup\$
    – Eric
    Commented Mar 13, 2013 at 13:27

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