According to the PIC16F886 datasheet (pdf warning), an instruction like bcf takes a single cycle. It's also described as a read-modify-write instruction, i.e., it reads a full eight bits, modifies that value, and then writes the modified value back to the memory/register/latch/whatever.

How can this all happen in a single cycle? At the very least, I would expect:

  • a cycle to read and decode the instruction
  • a cycle to read and modify the value
  • a cycle to write the modified value back.

I may be showing my 6502-centric thinking here, also I'm a software man and remarkably ignorant of electronics.

The same question could be asked also of comf, incf, rlf, and others.

  • 1
    \$\begingroup\$ That's because 1 instruction cycle on a PIC takes 4 clock cycles. So there is enough clocks in a single cycle (4 clock pulses) to do a decode, read and write. \$\endgroup\$
    – slebetman
    Commented Feb 12, 2022 at 19:38

3 Answers 3


You get a first clue in the datasheet where it states

  • DC - 20 MHz oscillator / clock input
  • DC - 200 ns instruction cycle

A 20 MHz clock has a cycle time of 50 ns, that's only 1/4th of the 200 ns minimum instruction cycle.

This means that a clock cycle is not the same as an instruction cycle on the PIC.

This means that one "instruction cycle" on the PIC takes 4 clock cycles. That's one reason, why most instructions are single cycle.

Additionally PIC has a Harvard architecture (code and data in different memories with separated busses, many microcontrollers and DSPs fall in this category) instead of the von Neumann architecture on most CPU based systems. So loading the next instruction does not have to wait until the last instruction has written its data back to RAM. It's an architecture decision that allows for a lot of freedom.

Different word-sizes for data and code: For example the PIC instructions are 12-bit words, so they can use part of the instruction word for "immediate data" which need not be loaded from RAM.

The memory bus is much less a limiting factor: Loading commands does not take up valuable memory bus bandwidth.

There are probably many more benefits I'm not listing here, but those are the main ones in my opinion.


Most PICs do as you said but each takes a clock tick and there are four clock ticks to an instruction cycle. A 4MHz chip executes 1M instructions per second. Some instructions take 8 clock cycles - like decrement-and-skip-if-zero and goto.

  • \$\begingroup\$ So it only uses 2 cycles out of 4? I see the potential for some optimization there. \$\endgroup\$ Commented Feb 11, 2022 at 13:22
  • \$\begingroup\$ It's been a long time but I think it is something like...(1) read instruction (includes address of target register) (2) read actual value from target register (3) execute instruction (4) write result to memory. That may not be exactly right but it is the concept for a PIC \$\endgroup\$ Commented Feb 11, 2022 at 13:32
  • \$\begingroup\$ No, it uses all 4 but only 2 are described above. For example (may not precisely apply to PIC) fetch/decode/execute/writeback, where execute reads and modifies, writeback does what it says. Of course higher performance processors optimise, e.g. fetching the (likely) next instruction while decoding the current one. \$\endgroup\$
    – user16324
    Commented Feb 11, 2022 at 14:23
  • \$\begingroup\$ @user_1818839: The PIC overlaps the execution of one instruction with a fetch of the next. I don't know what it does at every discrete moment during the execution of an instruction, but for something like ADDWF PORTB,f to work correctly, it would be necessary to have a definite time that PORTB is sampled and a definite later time when the new value is latched; for maximum reliability, there should also be an intermediate moment in time when the output from the first latch is resampled, and/or a later moment in time when the Z flag is computed based upon the value that was written back. \$\endgroup\$
    – supercat
    Commented Feb 11, 2022 at 21:38

So from my ASIC hacking experience + a quick look an the datasheet: instruction decoding, setting multiplexer paths + fetching data from registers or ram can be done in pure unclocked logic. Also modifying the bit. This means, it is possible to read and modify in no time from an SW perspective - it just needs some time to propagate the logic states through the chip. So you simply need a single clock to store back the result which might happen to be the same address as the data was fetched from.

I have programmed not a µC but similar complex logic clouds (like I call this) to not need to use to much clocks in my application. Works very well.

[Edit] Of course you should use as much tricks as possible to shorten the length of the chain of logic functions, so the synthesis tools for chip design can do their magic and everything works as expected. But modern synthesis tool are quite good in that. So if you code your µC or logic function too sloppy, it might not work in the end.

[Edit2] maybe you need a 2nd Clock for fetching the next instruction...

[Edit3] to accompany kruemi's post and extending mine: I am sure you also need one clock at least for the interrupt logic. I don't now if you can parallelise with the store-clock, so maybe here is a another clock you need (you need to have your interrupts evaluated before fetching the next instruction, as it might influence the instruction fetched)...

[Edit4] from an old book of mine, it states e.g. if the bcf command reads from a port, its latched first (another clock!)...

so from all my edits you already have 3-4 clocks needed, but only 1 is needed for what the command really does. the rest is just to do "management"

see https://files.learninginventions.org/Microprocessor%20(261214)/PIC%20Architecture%20Handout.pdf at Page 4 actually they use pipelining to accomplish 1 instruction per cycle at most until a branch is needed.


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