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I am a beginner in using FPGA and Quartus Prime Lite. I created a 32-bit adder using four 8-bit adders. These 8-bit adders were created using eight full adders.

I did the design using schematic .BDF files. After compilation the RTL viewer shows all the instances correctly, but the technology map viewer (post-fit) only shows four adders inside each 8-bit adder, not eight full adders as I designed. Can someone tell me the reason?

my design in RTL viewer

8-bit adder in RTL viewer

the four 8-bit adders in tech map viewer

8-bit adders with only four adders inside(four instances)

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For FPGA synthesis, your design can be entered in schematic form, as you have, or a Hardware Design Language (HDL) like VHDL or Verilog.

As part of being compiled, it has been synthesised. The synthesis tool will interpret your design and try to make a logic circuit from it, using the circuitry available in the target FPGA. That will be fitted into the FPGA, where particular logic elements will be allocated and the connections between them enabled.

When you view the Technology Map after fitting, you see the actual circuit it made to implement the design you entered. Your target FPGA implements combinatorial logic using LUTs, as most RAM-based FPGAs do. Each LUT has a single output and 4 inputs plus a carry input. So that's what it has available to make your combinatorial logic circuit out of.

Here, your adders are shown implemented in each of the single 4-input-with-carry LUTs your target device has available.

Because the input design (HDL or schematic) does not determine the actual circuit that will be made, the design is said to imply the circuit, not state it.

The synthesis tool will then infer the circuit from what was implied by the design.

(Remember to get the words right, many don't. It's: I talk and imply, you listen and infer.)

To get the most out of any target logic device, you have to understand the structure of it. When using a CPLD, FPGA or any IC, first read the datasheet to understand the internal design of it to some degree. Understand the resources available, what they can do and what they can't do.

In most RAM-based CPLDs and FPGAs, that's LUTs for combinatorial logic, registers for flip-flops and latches such as the D-type Flip-Flop (DFF), plus specialised circuitry such as PLLs, block RAMs and multipliers. Some use 4-input LUTs, others 6-input, some use individual registers, others in a mixture of capabilities and so on.

Otherwise, you can find yourself writing/drawing 'wish list' HDL or schematics, where you're designing a circuit that looks OK but can't actually be implemented to do what's needed e.g. a 1000-to-1 16-bit mux for 100 MHz operation in an FPGA. To avoid this, first understand what the IC is capable of, then move on to designing with your mind on how that will be implemented. It saves lots of problems later during synthesis.

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