How does Verilog treat multiple if blocks inside always_ff

If I have two if statements inside an always_ff block, such as:

always_ff @(posedge clk) begin
if (x >= 5) begin
// do something
end
if (x <= 7) begin
// do something
end
end


If x=6, which means both conditions are satisfied, will both if blocks get executed, or only the first one?

• Both get "executed". Remember, this is HDL, so both get "activated" in parallel. If they both assign to the same signal(s), the last assignment in the block will prevail. Commented Feb 13, 2022 at 4:32

All code within a begin/end block gets executed consecutively. When the first if condition is true, the statements inside the next begin/end block get executed consecutively. Then when the the second if condition is true, the statements inside the next begin/end block get executed consecutively.

When both conditions are true, you will have two sets of statement blocks executing consecutively. If your intent is to have only one block execute, then you should be using the else clause.

• With the clarification that the signals as seen from outside the block that are given new values inside the various if statements will not change more than once in a simulation cycle. The notion of consecutive execution applies only inside the always block. Commented Feb 13, 2022 at 12:19

There are 2 possible conditions here: 1) We are allocating values to the same register in both if conditions; 2) We are allocating values to different registers in the two if conditions.

1. If we are dealing with condition #1, i.e., allocating values to the same register (lets say "z") then: The second if condition would run as follows: The final value of "z" would be "2" after the clk posedge..

if (x >= 5) begin
z <= 1;
end
if (x <= 7) begin
z <= 2;
end

2. If we dealing with condition #2, i.e., allocating values to different registers in the two if conditions, then both if conditions would run as follows: We would have values for y = 1 and z = 2 after the clk posedge.

if (x >= 5) begin
y <= 1;
end
if (x <= 7) begin
z <= 2;
end


The rules for all Verilog behavior are set in the IEEE Std 1800-2017. Section 9.3.1 Sequential blocks, states:

A sequential block shall have the following characteristics: — Statements shall be executed in sequence, one after another.

In this context, a sequential block is defined by the begin/end keywords.

Also, section 10.4.2 Nonblocking procedural assignments:

The order of the execution of distinct nonblocking assignments to a given variable shall be preserved.

• The first one will also run, though. You don't say that it won't, but it's unclear. Commented Oct 17, 2023 at 1:21
• @Hearth yes you are right if we are allocating values to different register. Thanks for making that clear, I'll edit my answer. Commented Oct 17, 2023 at 12:34