There are 2 possible conditions here: 1) We are allocating values to the same register in both if conditions; 2) We are allocating values to different registers in the two if conditions.
If we are dealing with condition #1, i.e., allocating values to the
same register (lets say "z") then: The second if condition would run as follows: The final value of "z" would be "2" after the clk posedge..
if (x >= 5) begin
z <= 1;
end
if (x <= 7) begin
z <= 2;
end
If we dealing with condition #2, i.e., allocating values to different registers in the two if conditions, then both if conditions would run as follows: We would have values for y = 1 and z = 2 after the clk posedge.
if (x >= 5) begin
y <= 1;
end
if (x <= 7) begin
z <= 2;
end
The rules for all Verilog behavior are set in the IEEE Std 1800-2017. Section 9.3.1 Sequential blocks, states:
A sequential block shall have the following characteristics:
— Statements shall be executed in sequence, one after another.
In this context, a sequential block is defined by the begin/end keywords.
Also, section 10.4.2 Nonblocking procedural assignments:
The order of the execution of distinct nonblocking assignments to a given variable shall be preserved.