Unlike Xilinx which provides their users with a set of convenient
xpm_cdc_* modules, Lattice does not seem to have “the standard” way for clock domain crossing. So I have no choice other than write my own synchronizer.
In the Xilinx's world I'd use the
KEEP_HIERARCHY attributes to prevent the synthesizer from making destructive optimizations, and write some
set_false_path constraint alongside.
It looks like
/* synthesis syn_hier="hard" */ is the same thing as
KEEP_HIERARCHY, but, unfortunately, I found no mention of
ASYNC_REG in the Lattice docs.
What attribute (or combination of attributes) should I use instead?