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Is it possible to wire a graphics card to act as a PCIe host controller? I mean, assuming the firmware is also rewritten, is there anything in terms of hardware (EE) that prevents me from using a GPU to control a PCIe bridge as a host device?

More specifically - what hardware components are missing between a PCIE graphics card and a PCIE bridge, to allow the GPU to act as a PCIE host? What signals or bits are hardwired (ie burned to a chip) on graphics cards, that identify them as client devices on a PCIE bus, rather than a host?

Essentially, a single CPU core is different from a single GPU core by the implemented instructions and addresses. My understanding, is that, a CPU as we think of them today, is more than just a processor - it's more a SoC with some peripheral components that make it capable of communicating over the PCIE bus alone. For instance, communication over a PCIE bus is not a common feature of arm chips.

Perhaps a simpler version of the question, is "What do I need to implement between an arduino, which uses an arm processor, to make is a PCIE host?" I believe the answer to this question would be halfway to using a graphics card as a host.

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    \$\begingroup\$ It's impossible to say without inside design knowledge of the specific graphics card you have in mind. But the GPU's PCIe controller is likely implemented in silicon ("hard IP") and likely only supports endpoint mode. It would then not be possible even with firmware changes. \$\endgroup\$
    – TypeIA
    Feb 15 at 7:29
  • \$\begingroup\$ download.nvidia.com/open-gpu-doc/BIOS-Information-Table/1/… nvidia BIT contains a pointer to NVINIT_PTRS datastructure, which contains a PCIe Settings Script Pointer. Haven't actually found valid values or what it does, but maybe it's not that hardcoded? \$\endgroup\$
    – MishaP
    Feb 15 at 7:42
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    \$\begingroup\$ That does not mean much, just like a USB memory stick having USB descriptor tables does not mean you can turn it into a WIFI device just by modifying the descriptor tables... \$\endgroup\$ Feb 15 at 9:04
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    \$\begingroup\$ Also, I can't fathom why one would want to do this. Maybe this is an X-Y problem. What are you really trying to accomplish? \$\endgroup\$
    – TypeIA
    Feb 15 at 9:13
  • \$\begingroup\$ @TypeIA honestly, not sure yet... I'm experimenting/tinkering, but I'm more CS than EE, so I'm asking about the hardware side, although any insight on the firmware side is welcome as well. \$\endgroup\$
    – MishaP
    Feb 15 at 9:59

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You don't detail your platform, so it's unknown if this is on a standard PC motherboard or your own card backplane.

In any event, the PCIe bus needs a bus reset, PERST#, and the bus 100 MHz reference clock. Neither of these are output from a graphics card and the bus won't work properly without them. All PCIe bus agents derive their communications clocks from the reference clock.

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  • \$\begingroup\$ bus reset, PERST#, and the bus 100 MHz reference clock. a reference clock can be an additional chip between the GPU and the PCIE bus, right? PCIE bus reset is just a signal, something we can send from GPU or maybe even a switch? Not sure what PERST# is though. \$\endgroup\$
    – MishaP
    Feb 15 at 9:52

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