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I do have a chip where a pin can have multiple functions depending on the circumstances*. For clearness I'd like to have multiple pins in my symbol which all map to the same physical pad.

The other way around is easy (use @: GND@1, GND@2, etc.) but when I try to map multiple pins to one pad I find Eagle 6 doesn't let me do that because "It would exceed the number of pads in my package".

*In my example a TI SSL90S901B Ethernet PHY which has bootstrap configuration input pins to configure the chip on reset (with a 2.2k pullup/pulldown) and which are used for other things during operation (eg. LEDs). But this is a common thing. An AtMega88 for example combines SPI and normal GPIO-pins.

EDIT: I tried using wires in the symbol to create fake pins. This would have the benefit of making clear these pins are the same while still allowing multiple usages. However, wires in symbols seem to be completely ornamental in Eagle :(

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    \$\begingroup\$ This is normally handled by enumerating the options of interest within the pin name. You can also make versions of the schematic symbol customized to a given use. With the new textual storage format, you can even make such variants with a text editor. \$\endgroup\$ – Chris Stratton Mar 13 '13 at 20:53
  • \$\begingroup\$ Often only the first function (aka the default option) is used as a pin name. Use the signal name to properly identify the use of a pin in your system. The chip pin names themselves should never be board-specific. \$\endgroup\$ – spearson Mar 13 '13 at 22:40
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    \$\begingroup\$ Imagine that each pin in the sch has a drop down menu where one can select the function(s), which is used in a particular design. Tool tip shows the list of all functions for the pin. The old-fashioned way of showing all functions (P1.2/TA0.1/UCA0TXD/UCA0SIMO/A2/CA2) is enabled with a separate setting (global or component-by-component). Could be a neat feature. Cadence, Altium, CADsoft, KiCAD, are you listening? \$\endgroup\$ – Nick Alexeev Mar 13 '13 at 23:26
  • \$\begingroup\$ @spearson - I would strongly disagree with the idea that the chip pin names should never be board specific. Modern microcontrollers have such a plethora of I/O remapping options, that there could be a lot of benefit to customizing the name to include the function you are actually using. It's not the only approach, but it's a perfectly fine one. \$\endgroup\$ – Chris Stratton Mar 14 '13 at 1:30
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    \$\begingroup\$ This is a question of encapsulation. Creating parts is an expensive endeavour. It is time consuming and risky. PCBs have been scrapped from a simple part error. Parts should be created generically for maximum reuse and sharing. Naming pins with one design in mind breaks encapsulation, reduces part reuse, is a nightmare if the intended use of a pin changes, and without a standard naming practice makes the design more difficult in a peer review. \$\endgroup\$ – spearson Mar 14 '13 at 15:45
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No, you don't want to show multiple connections for the same physical pin on the schematic. This will lead to confusion because anyone else looking at the schematic will expect that each of those connections is actually a different physical pin.

You do this by listing all the possible pin functions in the pin name. For example, here is what my PIC 18F67J60 part looks like in a schematic:

First notice that power pins are at top and ground pins at bottom. That reduces some of the clutter around the remaining pins, and of course makes the schematic more clear on its own. In most cases, a circuit will only make use of one of the functions of each pin. It would be nice if there was a way to highlight the function or functions actually used, but removing the unused functions is worse. It can be quite useful to see what the part could have done or might do with different firmware.

Most of the time how a pin gets used is obvious from the schematic. One trick that greatly helps with this is to show logical direction for pins. I have little arrow symbols in Eagle just for that purpose. They are small and therefore don't get in the way, but help a great deal towards clarifying the circuit. Reasonable net names also help. Here is a small section of a schematic with the direction arrows and net names:

Particularly note the bottom two pins. Those are UART signals to another processor, so thereby are using the TX and RX functions of those pins. Each net can only have a single name, even though it will be the TX function (output) on one processor and the RX function (input) on the other. In this case I named the nets from this processor's point of view. This is the network processor within the overall device, so I named them NETTX and NETRX to help indicate the names are relative to this processor. However, there is potential for confusion at the other processor since NETTX will go into its RX pin and NETRX will go out of its TX pin. The arrows at the other processor will help a lot to head off a likely confusion.

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    \$\begingroup\$ I do much the same, but for pin counts above 40 or so, I generally try to split the chip up into some well thought out gates (I split them into gates, anyway. The "well though out" part is more a wish than a fact). It makes my schematics lay out much more understandably. \$\endgroup\$ – Scott Seidman Nov 14 '13 at 22:33
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As you said, the number of pins cannot exceed the number of pads in a package. Every library I have ever used does one of two things: names a pin nothing more than the simple "PA0" or "PB7" or lists every pin function in the name: "PB2 (MOSI/OC2A/PCINT3)". This name will show up on the schematic, but you could then manually change the name of whatever wire you connect to the pin with as "MOSI", "BUTTON_INPUT", "LED_OUT", etc. That way, you can use the same part for whatever design you are doing. As has been mentioned, customizing a part for use in a single board would be a huge waste of time.

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  • \$\begingroup\$ Actually, customizing a part can be faster than naming nets, especially when a large number of signals are involved. And, if not making physical-layout-driven symbols, there's also the issue of organizing pins by function - an organization that can vary drastically depending on which alternate function is in use. \$\endgroup\$ – Chris Stratton Mar 19 '13 at 14:36
  • \$\begingroup\$ But then you will have an increasing number of different versions of the same part. That defeats the purpose of being able to name a pin. EVERY design should have specific names for EVERY wire anyway, so it doesn't make sense to design specific parts every time you want to use a pin for a different reason. \$\endgroup\$ – Kurt E. Clothier Mar 21 '13 at 3:08
  • \$\begingroup\$ Could not disagree more! Your one approach, one symbol fits all way results in cluttered, unclear drawings. Mine enables the flexibility to present the key information where it is important. And if you think creating part variants is expensive, you are using antiquated tools. \$\endgroup\$ – Chris Stratton Mar 21 '13 at 4:24
  • \$\begingroup\$ At this point it would be a "to each his own" kind of resolution. All I can say is what I have seen done in 99% of every drawing I have worked with as well as every professional Library i have used. I am using Eagle as stated in the original question. Again, I have to stress that every professional organization I have ever worked with gives every wire in a schematic a unique name which is mapped to every node of the circuit it connects to. Creating part variants is not hard, it is just a waste of time when I can name a wire in the time it takes me to type it. \$\endgroup\$ – Kurt E. Clothier Mar 21 '13 at 7:20
  • \$\begingroup\$ If you don't place a visible label, the net name does not compensate for the lack of a function appropriate pin name in an offline viewing (ie, paper). If you do (or if your pin names list all possibilities) your drawings become too cluttered with fine print, often making it hard to clearly present what is going on. And the lack of ability to group multipurpose pins by utilized function remains. However, to each his own is a substantial improvement over the wording in earlier comments. \$\endgroup\$ – Chris Stratton Mar 21 '13 at 11:55

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