Traditionally dynamic logic has a clock input which determines whether the device will work in pre-charge or evaluation phase. PMOS is used as the pre-charge transistor and evaluation is done using NMOS. Is it possible to design dynamic logic using pre-discharge NMOS transistor and evaluation done using PMOS?

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    \$\begingroup\$ Take a look at these slides. To investigate further search "zipper cmos logic". \$\endgroup\$
    – Syed
    Commented Feb 16, 2022 at 4:54
  • \$\begingroup\$ Thanks @Syed, the slides were helpful. \$\endgroup\$
    – xyx123
    Commented Feb 16, 2022 at 20:02

1 Answer 1


Yes, that is certainly possible, as long as propagation delay and/or circuit area are not important design constraints. Since this sounds a bit like a homework question I will leave it at that.


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