I'm designing a Hartley oscillator using a MOSFET, but I have some issues. I've chosen L1 as 3 times L2 to obtain a gain of 3, however, it's more like 2.4.

hartley oscillator circuit

First of all, I can't understand why the GATE voltage is not a perfect sinus like the OUT voltage. Maybe the gain loss could be caused by this dirty voltage?

v(gate) and v(out) waveforms

v(gate) peak-peak

v(out) peak-peak

Can you see errors in my design? I can't find the solution to this problem. I also tried to reduce the minimum step for the .tran analysis to reduce the error in my FFT of v(out), it presents some harmonics, however, it doesn't seem so dirty.

v(gate) and v(out) fft

Thanks in advance for your help.

  • \$\begingroup\$ Either you're not showing everything or you've made some changes because, as it is, the schematic will not oscillate. \$\endgroup\$ Commented Feb 16, 2022 at 10:18
  • \$\begingroup\$ Hi, all you can see it's referred to the images shown above, I didn't change anything. Why it wouldn't be oscillate at all? \$\endgroup\$
    – nor_gate
    Commented Feb 16, 2022 at 10:37
  • \$\begingroup\$ It does't oscillate for me. BTW, using anything numdgt>6 enables double precision for the data file (the .RAW file), so setting it to 20 is just the same as 100. \$\endgroup\$ Commented Feb 16, 2022 at 13:39
  • \$\begingroup\$ I'm sorry, I didn't attach the physical parameters of my transistor because they are not showed in the spice directives, however myNMOS l=2u w=10u ad=24p as=24p pd=14.8u ps=14.8u \$\endgroup\$
    – nor_gate
    Commented Feb 16, 2022 at 17:24
  • \$\begingroup\$ So it was the first one, then. ;-) To show them in the schematic Ctrl+RClick on the NMOS and 2xClick on the relevant lines to add an X. The are 4 lines that can be used to show various parameters, and the order doesn't matter (in this case), since they will all be concatenated into one line. For example use View > Netlist and you'll see all the settings in the symbol appearing in one line. \$\endgroup\$ Commented Feb 16, 2022 at 18:08

3 Answers 3


The original Hartley oscillator had a single coil with a tap - the coil worked as a transformer. Separate non-coupled coils can also lead to a working oscillator with modern components which have substantially more gain than the triode valves had 100 years ago. But that was not the original idea of the Hartley oscillator.

Have you used perhaps the equations for the single tapped coil version? That and any other calculation details cannot be decided by reading the question. Another possible reason for the voltage calculation inaccuracy is that the fet input also loads the feedback circuit, it's far from an ideal infinite input impedance amp if your model is realistic. Unfortunately I do not know well enough how to interpret properly what's programmed into your mosfet model.

About the distortion:

Your oscillator doesn't have any other amplitude stabilization than distortion in the amplifier. When the oscillation starts the amplitude grows until the mosfet amp starts to distort so badly that it's effective gain has dropped just to the amount needed to compensate the attenuation in the feedback path.

The output can look sinusoidal, but it's not. The resonant circuit attenuates distortion components but it cannot fully remove them.

The input capacitance of the mosfet is highly nonlinear (=changes radically along Vgs and Vdg) in large signal operation; do not expect sinusoidal Vgs even in case the input capacitance is charged and discharged by a sinusoidal current.

BTW the input capacitance of mosfets is so complex that the manufacturers more likely specify the amount of total charge needed to input and output to the gate if one wants to turn the mosfet fully conductive and then back to non-conductive.

Low distortion oscillator which doesn't need extra filtering stages to remove the distortion can be got by using low distortion amp and by inserting an AGC (=automatic gain control) circuit which reduces the loop gain as the signal amplitude grows and that's designed to affect before the amp starts to distort too badly.


The distortion is probably caused by the Miller effect together with the so called "Miller-Plateau" characteristic of MOSFETs.

The input capacitance of a MOSFET depends not just on the gate to source capacitance but also the gate to drain capacitance and the output voltage at the drain. That will cause the effective input capacitance to vary over the sine wave cycle.

If the amplifying stage was adapted to a cascode configuration or another arrangement that minimized the feedback from the drain the effect would be reduced.

Also you don't show any mutual coupling between the two inductors that would make them into a transformer. That is required for it to be a classic Hartley oscillator configuration.

MOSFET Gate Charge Power MOSFET Basics: Understanding Gate Charge


Try this:

I was wondering what one would look like, too,, so I tried something.

MOSFET Hartley


Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.