My question is about how you should declare Verilog arrays. As far as I read till now arrays in Verilog can be declared in two ways:
- Like this:
- Or like this:
Before posting this question I read this page.
I read here that 7 is the most significant bit and 0 is the least significant bit. Nevertheless, I am still a bit confused. More precisely, my confusion is about whether there is an internally different representation of the bit array, depending on how you declare it, and that would be either big-endian or little-endian.
I ask this question because if my assumption is true then, depending on how you declared the bit array, when you want to access the bits in it you must take care of the way you access them, from left to right or right to left.