Does declaring Verilog arrays with indices in different directions makes any difference?

Question

My question is about how you should declare Verilog arrays. As far as I read till now arrays in Verilog can be declared in two ways:

1. Like this: array1[0:7]
2. Or like this: array2[7:0]

Before posting this question I read this page.

I read here that 7 is the most significant bit and 0 is the least significant bit. Nevertheless, I am still a bit confused. More precisely, my confusion is about whether there is an internally different representation of the bit array, depending on how you declare it, and that would be either big-endian or little-endian.

I ask this question because if my assumption is true then, depending on how you declared the bit array, when you want to access the bits in it you must take care of the way you access them, from left to right or right to left.

Answer 1

I think you might be confusing bits with array index. Also, you did not show your complete array declarations. Assuming you declared your arrays as 4 bits by 8 elements as follows:

module tb;

reg [3:0] array1 [0:7];
reg [3:0] array2 [7:0];
integer i;

initial begin
    for (i=0; i<8; i=i+1) array1[i] = i;
    for (i=0; i<8; i=i+1) array2[i] = 2*i;
    $display("array1[2] is ", array1[2]);
    $display("array2[4] is ", array2[4]);
end

endmodule

Then, it does not make much difference if 0 is to the left of 7, or vice versa, in your declaration. As you can see, you can assign to or access an array element using a simple index variable (i).

This prints:

array1[2] is  2
array2[4] is  8

Refer also to the IEEE Std 1800-2017, section 7.4 Packed and unpacked arrays.