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I've noticed a few component packages now that have small "tabs" on the sides of their exposed pad (thermal pad). One example is the Analog Devices ADM7154 LDO:

enter image description here

Note the 0.356 x 0.457 mm tabs on the left and right sides of the exposed pad.

  1. Why does the package have these tabs?
  2. Should the PCB footprint / land pattern also have these tabs?
  3. If so, and they're omitted from the PCB footprint, will this have any serious effects on reflow solderability, thermal or electrical performance?
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    \$\begingroup\$ Probably related to how the exposed pad is physically connected to the rest of the internal lead frame. The PCB pad does not need to follow that exact shape, and no, the difference won't have any measurable effect. \$\endgroup\$
    – Dave Tweed
    Feb 17 at 19:00
  • \$\begingroup\$ Wouldn't the data sheet tell you what the recommended land pattern is? \$\endgroup\$ Feb 17 at 19:52
  • \$\begingroup\$ @ScottSeidman I linked it, have a look. (TL;DR: No, not always.) \$\endgroup\$
    – TypeIA
    Feb 17 at 20:09
  • \$\begingroup\$ Manufacturers account for some amount of incomplete contact between the exposed pad and the land underneath it. It's more than you might expect - 25% or so IIRC. So electrically and thermally, those little extra areas will have no significant effect on performance. \$\endgroup\$
    – vir
    Feb 17 at 20:14
  • \$\begingroup\$ The example layout they show in the data sheet has no tabs \$\endgroup\$ Feb 17 at 21:11

2 Answers 2

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I can't speak for all manufacturers, but sometimes thermal pad is the bottom of the die carrier, as that ensures thermal performance. Die carriers could be fed from a reel, that has stamped die carriers attached by thinner elements that are cut on unreeling. Those small tabs would be what remains of the die carrier holder.

You don't have to put the feature in the footprint, as it's likely solder won't flow well in the area, due to it's surface tension, but you shouldn't put exposed copper for other signals or vias there.

TL;DR:

Die carrier reel

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The exposed pad, AKA paddle, is often used as a thermal interface to the PCB.
On the other hand, a lot of ICs that don't dissipate a lot of power, it's part of the package and often connected to some voltage rail such as ground. You'll find paddles on low power ICs typically on leadless packages.
Some ICs use paddles for high current connections and may have multiple paddles.
It's best to check the data sheet what you should do with this pad.

In your particular case, the paddle is used as a thermal interface as discussed on page 6 of the data sheet you linked to. Information on the PCB layout is shown on page 21, more thermal considerations on page 18.

The small tabs on the paddle are generally not part of the PCB footprint. You should used the manufacturer's footprint recommendation or lookup the footprint for a JEDEC MS-012-AA.

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  • \$\begingroup\$ Thanks, I deleted my first comment and +1 for the footprint link, appreciated. \$\endgroup\$
    – TypeIA
    Feb 17 at 19:36
  • \$\begingroup\$ If the tabs are specified on datasheet, then they shouldn't be completely ignored. No need to copy that to the copper area, but a keep out area is needed. In this case of course you are using SOIC, so you are probably not out of space and wouldn't be putting anything so close to the pad anyway. \$\endgroup\$
    – Ralph
    Feb 17 at 19:46
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    \$\begingroup\$ I'm curious--is "paddle" meaning the exposed pad a common word just in certain regions or languages, or is it just by chance that I've never yet come across it anywhere other than stackexchange (with its large international community)? I've always kind of wondered each time I see it, but for whatever reason never bothered actually asking until now. \$\endgroup\$
    – Hearth
    Feb 17 at 19:52
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    \$\begingroup\$ @Hearth I've come across "paddle" in the IC packaging realm in the U.S. 20 years ago. The terminology has stuck with me due to that exposure. \$\endgroup\$
    – qrk
    Feb 17 at 22:25

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