Reverse current blocking - how do these dual FETs work?

Question

I have a fairly simple application:

Q1 is a P-Channel MOSFET. It had a flyback diode between drain and source (which is not illustrated here.)

Between ST1 and ST2 there is a 1k resistor to load the circuit by 5mA (BT provides 5V output.)

Unluckily, BT1 is providing negative voltage when it is turned off (-3V.)

I came across with this circuit by TI:

I have some question about this, and I couldn't really find answers:

1. What kind of MOSFETs are being used? (N or P channels?) I believe they should be P-channels, as their arrow is pointing out from them. However, in my diagram, the arrow is pointing towards the source while these are pointing towards the drain.
2. Is this only a drawing difference? In other words, which one of these two would be my Q1? The left one or the right one? (I believe right one based on the flyback diode.)
3. I can understand how this blocks reverse current when the gates are on GND. When they are opened up, I understand the right FET: current flows from source to drain (from left-to-right on the figure,) but what happens with the left FET? Why would current flow from drain to source in a P-FET?

Answer 1

Those are nFETs with back to back drains. Unfortunately, the arrows are inconsistent when they point into the substrate vs out of the source:

Sourced from https://www.electronics-notes.com/articles/electronic_components/fet-field-effect-transistor/mosfet-metal-oxide-semiconductor-basics.php.

With that out of the way, this is really a different circuit algorther. In a reverse current situation, current is indeed flowing from source to drain through the body diode of the right FET, but it is stopped by the body diode of the left FET as long as the control voltage at the gate is low.

You may wish to consider a back-to-back pMOS pair instead:

^{simulate this circuit – Schematic created using CircuitLab}

When BAT1 is providing forward voltage, your switch controls your back to back FETs -- closing the switch pulls the gate down to ground, turning both of them on and conducting right through their channels (there is not a diode drop from supply to load).

When BAT1 is outputting -3 V, then the gate is high relative to the leftmost source, so the left FET doesn't conduct. However, its body diode could be forward biased, which is why the right FET is necessary - its source is also pulled to ground by the load, preventing it from turning on. Its body diode is also oriented to not allow -3 V to be applied to the load.

Here's the plot showing the output voltage as the battery voltage is swept from -3 V to 9 V with the switch closed:

With the switch open, the load voltage is always 0.

Note: The schematic was updated to incorporate a small change to the FETs (back to back sources rather than back to back drains and the resistor is moved) in order to make this circuit more robust in different scenarios such as back-feeding with multiple supplies.