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The input driving below circuit has only two states: \$-10V\$ for OFF and \$0V\$ for ON. Why can't we apply this input directly to the gate? I mean removing the resistor \$R_G\$ doesn't seem to change anything?

I understand \$R_D\$ is there to ensure the jfet is in hard saturation, operating in ohmic region.

But I don't get the role of \$R_G\$. It is not part of voltage divider bias or anything. It is simply shorted to the ground. Why can't I remove it? (Maybe removing \$R_G\$ even helps here.. as the the input impedance of jfet gate is very high, so the input signal doesn't have to provide much current.)

Source: https://archive.org/details/ElectronicPrinciples8thEdition/page/422/mode/2up?view=theater

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  • \$\begingroup\$ Does this answer your question? electronics.stackexchange.com/questions/60427/… \$\endgroup\$ Feb 18 at 6:44
  • \$\begingroup\$ @LarsHankeln no it doesn't. The answer you linked is more about the turn-off or gate floating prevention of power MOSFETs. This question, however, is about biasing the N channel JFETs. \$\endgroup\$ Feb 18 at 6:46
  • \$\begingroup\$ Could you please link the source of the info? Textbook? Website? It seems that this is about self biasing but I reckon there should be a resistor between the JFET's source and the ground to provide proper biasing. Normally RG is there to make the JFET's gate grounded. It's high enough not to load the source. \$\endgroup\$ Feb 18 at 6:50
  • \$\begingroup\$ @RohatKılıç yeah this would be self biasing if there were a resistor at source terminal. I think this is just a direct gate bias meant for switching circuits. Not for active region operation. I'll link the textbook, one sec... \$\endgroup\$
    – across
    Feb 18 at 6:53
  • \$\begingroup\$ @LarsHankeln I'm going through that link... haven't started MOSFET yet but that link is interesting, it seems to suggest Rg makes the switching faster somehow.. \$\endgroup\$
    – across
    Feb 18 at 6:57

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The image shown in the textbook and the one shown in the question body are different:

enter image description here

The image above is what the textbook mentions (fig. 11-7a). But the arrangement shown in the question body is totally different than this.

They might have been made a mistake while drawing the image. If there's one positive source you can't bias an n-ch JFET unless there's a resistor tied to the source pin. In self-bias or divider-bias you can ground the gate with a resistor but there must be a resistor tied to the source.

There's nothing wrong with this arrangement since the source is grounded and a negative voltage should be applied to the gate for proper biasing.

The purpose of RG here is to provide a path for the bias so that an AC signal can be coupled to the gate:

enter image description here

Image Source

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