0
\$\begingroup\$

I wanted to ask for some help regarding the setup of a 555 timer. I'm using it in the standard monostable mode, running at 5 V, basically as a 1 min timer, using a simple momentary pushbutton to trigger.

Now what I want to accomplish is that when triggered (meaning the output is now high for 1 min), if I actuate the momentary switch again during this 1 min high period, I reset the timer for an additional 1 min. So let's say I trigger the 555, and 30s later I hit the switch again, I'd like the output to now stay high for a cumulative 1:30 min. Is there a simple way to achieve this, perhaps with some additional transistors/MOSFETs and capacitors? Surely there already exists a neat solution for this "retrigger when already triggered to extend timer" mode of action? Ideally it would stay HIGH during the whole time, but it is OK if it goes HIGH-LOW-HIGH during the retrigger, as long as it is 'automatic', with no additional switch inputs.

For what it's worth, I tried (simulating at falstad.com) a simple P channel mosfet across the timing capacitor, with it's gate connected to the trigger pin, so every time the trigger is actuated, it sees a ground pulse, but it doesn't fully discharge the timing capacitor (only takes it down to ~2V, I guess due to GS threshold voltage)?

EDIT Well I retried the same setup as above (bridging the timing capacitor) with a PNP transistor this time, and it works perfectly, well almost, now pulling the timing cap all the way down to ~0.6V. Can someone explain why the transistor is pulling lower than the mosfet, I guess it's to do with the difference in 'threshold voltage', the mosfet requiring a higher difference between gate and source than the transistor between base and emitter?

I guess this can also be called a "Missing Pulse Detector" circuit for the 555.

Thanks for any help!

\$\endgroup\$
5
  • 1
    \$\begingroup\$ Put a npn transistor across the timing capacitor and drive the npn transistor with a pnp transistor from the trigger input. Both transistors require base resistors. Connect emitter of pnp to Vdd. \$\endgroup\$
    – James
    Feb 18 at 21:06
  • \$\begingroup\$ Thanks for the reply! I thought of the PNP-NPN combination, as it would be a low side switch, and I guess your suggestion would pull it all the way down to 0V. But if I just put a single PNP in the same place and run its base off the trigger, it also dumps the timing cap, albeit only to 0.6V, which is still good enough (running at 5V Vcc, that 0.6V difference doesn't make up much time) \$\endgroup\$
    – parkside
    Feb 18 at 21:08
  • 1
    \$\begingroup\$ Almost to 0V, short of 0V by Vce(sat). \$\endgroup\$
    – James
    Feb 18 at 21:10
  • 1
    \$\begingroup\$ one minute is kind of long for a 555. accurate capacitors of appropriate size are expensive, consider a counter-based timer such as CD4060 instead. \$\endgroup\$
    – Jasen
    Feb 18 at 22:37
  • \$\begingroup\$ See updated answer. \$\endgroup\$
    – AnalogKid
    Feb 18 at 23:00

2 Answers 2

2
\$\begingroup\$

What you tried will work better if you use a small PNP such as a 2N4403 or 2N3906 instead of a FET. This should pull the timing cap down to around 0.6 V if the base is pulled all the way down to 0.0 V. Note that 0.6 V is over 10% of the charging voltage, so the subsequent time period after the switch is released will not be the full 1 min.

Beyond that . . .

You have discovered what we all run into eventually - the 555 "monostable" circuit isn't. It isn't a true monostable (among other things, it has no positive feedback to guarantee operation), it isn't a normal retriggerable, and it isn't a normal pulse-stretcher.

The grunt solution is two small n-channel MOSFETs such as the 2N7000. One to discharge the timing cap all the way down to 0 V, and one to invert the logic polarity of the trigger signal to drive it.

Two, 1-FET inverters in series, with the first one's gate tied to the Trigger pin and signal, and the second one's drain tied to the timing R-C node. The drain-gate connection in the middle is pulled up to Vcc with 10K - 100K.

Update:

Can someone explain why the transistor is pulling lower than the mosfet, I guess it's to do with the difference in 'threshold voltage', the mosfet requiring a higher difference between gate and source than the transistor between base and emitter?

You are correct. For the 2N7000 (a very common small MOSFET for these kinds of applications), the typical Vth is 2.1 V; compared to a 2N4403 Vbe of 0.6 V. Assuming your p-chanel MOSFET is similar. when the gate is pulled down to 0 V (and the drain is grounded), the source will be at 2.1 V (typically). That leaves enough charge in the timing capacitor to shorten noticeably the following timing period.

That Vth is larger than Vbe is very handy sometimes, but not in an emitter-follower vs. source-follower situation.

\$\endgroup\$
1
\$\begingroup\$

This is not posted as an answer to your question: How to 'retrigger' 555 timer.

A 555 used as a 60-sec monostable will have a wide timing tolerance because of the large R and C values needed. The large R will be influenced by leakage currents. The large C will be a wider tolerance part. You're also having to add more parts around the 555 to produce the function you want, so it's moving further from a standard 555 circuit. This makes it a smaller step to use an alternative circuit.

Instead, this is a recommendation to use the below circuit for greater accuracy with little increase in cost and part count. It meets the requirement of driving its PULSE output HIGH for 60 secs after SW1 was last released, extending any previous PULSE as necessary.

The circuit uses a 74HCT4060 Counter With R-C Oscillator as its timing element. This IC contains an oscillator for external R-C, which drives its internal 14-bit ripple counter. That allows a smaller capacitor with a good tolerance to be used in the timing circuit, with its frequency divided down by 8192 by taking the timing taken from its slowest counter bit, Q13.

As a bonus, the fastest counter bit (Test Point, TP) can then be observed on a 'scope to check and measure the oscillator frequency. This saves you waiting for 60 secs every time, in testing, debugging or any calibration of the R2 value.

On power-up, the 74HCT74 D-type Flip-Flop (DFF) output Q (PULSE) is cleared to LOW by a pulse from R4 and C2. D1 ensures C2 is discharged quickly on power-down and does not drive a voltage into ICs that's much higher than their falling VDD.

When SW1 is pressed, it presets the DFF Q output (PULSE) HIGH and restarts the monostable counter. If SW1 is pressed during the monostable period, the counter is restarted so the 60 seconds starts again.

When the counter reaches 8192 and its Q13 bit goes HIGH, it clocks a LOW into the DFF, which ends PULSE. Note that the counter is left running when PULSE has ended. Further Q13 rising edges will just harmlessly clock LOW into the DFF again and again.

The 74HCT4060 datasheet details how its oscillator component values are arrived at. In short, the oscillator frequency is 1/(2.5 x R2 x C1) and R1 is to be at least double R2. The shown values give a monostable period of 59.68 seconds and a TP frequency of 17.159 Hz (58.28 ms). Both are nominals and don't consider part tolerances.

schematic

simulate this circuit – Schematic created using CircuitLab

Switch bounce will simply generate more presets/clears so the switch does not strictly need debouncing. If a changeover push switch is used, the other DFF in the 74HCT74 can debounce the switch, as shown below.

The monostable's 60-second period starts when SW1 is released. If you want this to start when the switch is pressed, a falling edge detection circuit can be added between the switch and the ICs or on the debounce DFF output. The latter is shown in the schematic below, which will produce a 260 us mins pulse.

schematic

simulate this circuit

Note the repeated use of the same component values where possible, to simplify the parts list. If the monostable timing RC values are changed, the other positions using the same values can be reconsidered also. The exception is the switch resistor, as it should have a larger 'wetting' current through its contacts.

\$\endgroup\$
1
  • \$\begingroup\$ The first circuit will also work just fine from 3-18V when using a CD4013 instead of 7474, and a CD4060. The polarity of the PRE/CLR inputs is reversed though (they are active high on the 4013). \$\endgroup\$ Feb 20 at 1:07

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.