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The input rising and falling edges occur at time t = 0. The propagation delays of the respective gates are 3 and 4 ns, as shown.

According to my analysis, the waveforms are as below:


As I've drawn above, I don't think there's any glitch in the final output Y2, since both the inputs i1 and i2 have a transition at t = 0; and if there was to be a glitch, it would have been at t = 4 only if the 2 inputs to the AND gate were High before t = 0.

But since Y1 is Low before t = 0 and turns High only after t = 3, and by the time Y1 goes High, the other input i2 is already at Low. So there is no glitch in output Y2.

Is this correct? Or am I missing something here?


A proper propagation-time specification for a gate should state the guaranteed minimum time and the guaranteed maximum time. Although simulators don't usually do so, I would suggest that you should model an OR gate with a 1ns minimum propagation and a 3ns maximum propagation as being:

-1- High if, within the last nanosecond, either input has or had been at a valid high level for at least solid nanoseconds.

-2- Low if, within the last nanosecond, both inputs have or had been at a valid low level for at least three solid nanoseconds.

-3- Indeterminate in all other cases.

Thus, if the OR gate in the above diagram had a 1ns minimum and 3ns maximum propagation, the output would have been low from time 0-1, indeterminate from time 1-3, and high thereafter.

Until time 1, the AND gate would have had its first input low (and its output would be low). Until time 2, it would have "within the last nanosecond" have seen input 0 low for at least four solid nanoseconds. At time 2, its output would go indeterminate until at time 4, it would again have an input that was low for four solid nanoseconds.

Thus, the output of the AND gate should be regarded as low until time 2, indeterminate from time 2-4, and low after time 4.

Note that if this approach indicates a circuit will work reliably, it will do so, but there are many circuit designs which will delay into having "indeterminate state" everywhere even though in reality they would have useful behavior. Such problems may often be solved by assigning minimum propagation delay values which are very close to the maximum values. This is not entirely realistic, and introduces the possibility that a circuit may simulate correctly but fail in the real world. On the other hand, it's often necessary to tweak only a small number of circuit elements in such fashion; if one can validate the real-world behavior of those few elements while having the rest of the elements behave "more sloppily" than real-world circuits, one should be fairly confident that signals which are reported as high, will be high, and those that are reported as low, will be low (those that are "indeterminate" could in reality be valid high, valid low, oscillating, sitting at mid-rail, or anything else).

Note that many simulations assume either an "inertial model" or a "transport model" for propagation delays. The inertial model assumes that an output will not appear to change until the apparent correct value has been stable for a duration equal to the propagation delay. The transport model assumes that the reported state of an output will represent its computed state based upon the value the inputs had some time before. If an inverter has a 10ns propagation delay with the inertial model, a 6ns pulse on the input will represent nothing on the output, while an 15ns pulse would cause a 15ns pulse to appear on the output that was delayed by 10ns. Under the transport model, that same 6ns pulse would cause a 6ns pulse to appear on the output delayed by 10ns (such that the output would first switch 4ns after the end of the pulse), and the 15ns pulse would appear the same as with the inertial model. Neither model, unfortunately, generally has any provision for timing uncertainties.

  • \$\begingroup\$ Good detailed answer. See also "inertial delay" typical of gates vs "transport delay" typical of routing delay. \$\endgroup\$ – user_1818839 Mar 14 '13 at 16:36
  • \$\begingroup\$ @BrianDrummond: The behavior of real circuits is often somewhere between what would be predicted by the "pure transport delay" and "pure inertial delay" models. Further, a problem with such models is that they lead to simulated behaviors which are more predictable than real-world behaviors, when it would be better if the reverse were true. Still, it may be worth mentioning them in my answer. \$\endgroup\$ – supercat Mar 14 '13 at 17:19

There is a race; the current test stimuli simply don't find it. Increase the test coverage systematically and it ought to be detected.

  • \$\begingroup\$ Yes. I know that, for eg., if the two inputs i1 and i2 were exchanged, there would be a High pulse glitch for about 3ns on the output. But I wanted to clarify that there wouldn't be any for this input combination. \$\endgroup\$ – potato_in_my_ear Mar 14 '13 at 11:39
  • 1
    \$\begingroup\$ If the gates are guaranteed to have a propagation delay which is exactly equal to the specified time, the circuit could be guaranteed not to have an output glitch. Any testing which assumes that the propagation delays are exact thus shouldn't find a problem. The fundamental real-world question is whether the "or" gate is guaranteed to generate enough delay before its output rises that the "and" gate will have recognized the other input as "clearly low" before that happens. \$\endgroup\$ – supercat Mar 14 '13 at 16:30

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