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I am trying to understand the correct way to calculate throughput of a digital hardware design block that forms part of a bigger system.

Here are the few scenarios:

  1. DUT takes 10 clock cycles to generate 20 bit output, then another 10 clock cycles to generate the next 20 bit output. -> The maximum throughput is 20 bits per 10 clock cycles = 2 bits/cycle

  2. DUT takes 10 clock cycles to generate the first 20 bit output, then (being pipelined) it generates a new 20 bit output ever cycle -> The maximum throughput is 20 bits per 1 clock cycles = 20 bits/cycle

Is this correct or do I have to involve clock frequency to calculate the throughput as well?

EDIT:

DUT = Device-Under-Test is the sub-block for which I am trying to calculate the throughput. This can the design as a whole i.e system level, or a single block inside it that generates data.

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  • \$\begingroup\$ That is a very theoretical conclusion and not enough information to accurately answer, but I would say that from the supplied limited information available your assumptions are correct. As for the involvement of clock frequency it is obvious that any system as its own maximum permitted clock frequency, hence, yes, you would have to consider your circuit maximum clock frequency. \$\endgroup\$ Feb 20, 2022 at 22:34
  • \$\begingroup\$ I am confused about how to calculate throughput, what information is missing? Is the block sourcing data to the DUT or the one sinking data from the DUT? \$\endgroup\$
    – quantum231
    Feb 20, 2022 at 22:37
  • \$\begingroup\$ Let me know what you mean by DUT and Block. DUT means Device Under Test. What do you mean by Block ? is the DUT part of the Block ? Is the DUT the actual Block ? Please refine with details. \$\endgroup\$ Feb 21, 2022 at 0:13
  • \$\begingroup\$ The question has been refined with some details. \$\endgroup\$
    – gyuunyuu
    Feb 22, 2022 at 13:00

2 Answers 2

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You have it correct. But for a lot of applications you don't think about number of bits, but rather number of values, like the output of a multistage filter.

So for your example 1), I would describe that as 1 20-bit value every 10 clock cycles. I would not describe that as 2 bits every clock cycle.

For your example 2) you would have 10 clock latency (pipeline delay) for the first value, then you get a new value every clock cycle. Your overall throughput would be a tad smaller than 1 value per clock cycle.

Now if you give that clock a frequency, for example 100 MHz, then you can say that your overall throughput is 10 MHz in the first case, and bit less than 100 MHz in the second case.

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  • \$\begingroup\$ If someone was to ask to calculate and present the actual value of the throughput, what does that come to? i.e what is the proper scientific way to express throughput in such a case? \$\endgroup\$
    – quantum231
    Feb 21, 2022 at 20:35
  • \$\begingroup\$ It depends on the application; on the requirement as to what measure is relevant. In the case of a filter, it may be 10 million values/sec, with each value being 16 complex multiply adds. Or maybe it's having a new complex value available every 100 ns. \$\endgroup\$
    – SteveSh
    Feb 21, 2022 at 22:09
  • \$\begingroup\$ In the case of some of the application's I've worked, it might be needing to compute 2000 complex values in a couple of hundred microseconds. IMM, there is no one, "proper" way to do this. \$\endgroup\$
    – SteveSh
    Feb 21, 2022 at 22:12
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You have it basically correct. Multiply bits/clock by clock rate and you have throughput.

The other important idea that comes up is latency, that is, the number of cycles from input to output.

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  • \$\begingroup\$ Wouldn't that be the 10 clock cycles OP in example 2? \$\endgroup\$
    – SteveSh
    Feb 21, 2022 at 1:05
  • \$\begingroup\$ In both cases latency is 10 cycles. \$\endgroup\$ Feb 21, 2022 at 1:34

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