I am using Xilinx VC707, I need to input data from SFP port and send it out on ethernet Phy (RJ 45) and vice versa at 1G. I instantiated two PCS/PMA core (1G/2.5G Ethernet PCS/PMA or SGMII v16.0), MAC and UDP core (open source) each for SFP and Ethernet Phy.

While configuring PCS/PMA core for SFP side I set "include shared logic in core" and for Ethernet side "include shared logic in example design" and connected all output clocks of SFP PCS/PMA core to input clocks of Ethernet PCS/PMA core. I can understand that clock for GMII data for MAC of SFP is "userclk2_out". But I am failing to understand what clock is to be used for GMII data for MAC of Ethernet?

As per 1G/2.5G Ethernet PCS/PMA or SGMII v16.0 Clock for client MAC k is derived from sgmii_clk_r and sgmii_clk_f using ODDR primitive.

SGMII Clcok generation

As per example design of "include shared logic in example design" clock for client MAC (for ethernet) can be generated using this code .


But when I use ODDR to generate client clock "sgmii_clk" which I need to provide to MAC of ethernet it gives following error on Vivado

[DRC REQP-1884] ODDR_has_invalid_load: ODDR cell sgclk_ddr_iob loads should only be an output buffer or a port, but it is driving an invalid load (one or more of):sgmii_clk_BUFG

How to use ODDR output inside sub modules without connecting it to output buffer or port?


1 Answer 1


Use an iobuf to bring the oddr internal signal back out into the fabric from the internal iob.

There is a similar suggestion here (see the comment by Nathan B): https://www.fpgarelated.com/showthread/comp.arch.fpga/82848-1.php

I would also put it on a clock buffer in order to use the internal signal as a clock.

Don't know if the timing analysis produced by something like this will have any meaning.

  • \$\begingroup\$ Yeah you are right it is not possible, but is there any other primitive which act like DDR for internal logic because I need this clock to drive MAC and UDP core. Xilinx example design also take out ODDR output to pin and comment that as "clock for client MAC" but logically speaking after PCS, MAC module should be in same FPGA but without stable clock for GMII data achieving throughput is not possible. \$\endgroup\$
    – optiplex91
    Feb 21, 2022 at 19:27
  • \$\begingroup\$ Thanks @Mikef, it is working. I take output of ODDR to input of IOBUF, IO pin of IOBUF with top level port, and output pin of IOBUF with new wire and use that new wire for other modules. direction or T of IOBUF is low \$\endgroup\$
    – optiplex91
    Feb 22, 2022 at 5:54

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