I am using Xilinx VC707, I need to input data from SFP port and send it out on ethernet Phy (RJ 45) and vice versa at 1G. I instantiated two PCS/PMA core (1G/2.5G Ethernet PCS/PMA or SGMII v16.0), MAC and UDP core (open source) each for SFP and Ethernet Phy.
While configuring PCS/PMA core for SFP side I set "include shared logic in core" and for Ethernet side "include shared logic in example design" and connected all output clocks of SFP PCS/PMA core to input clocks of Ethernet PCS/PMA core. I can understand that clock for GMII data for MAC of SFP is "userclk2_out". But I am failing to understand what clock is to be used for GMII data for MAC of Ethernet?
As per 1G/2.5G Ethernet PCS/PMA or SGMII v16.0 Clock for client MAC k is derived from sgmii_clk_r and sgmii_clk_f using ODDR primitive.
As per example design of "include shared logic in example design" clock for client MAC (for ethernet) can be generated using this code .
But when I use ODDR to generate client clock "sgmii_clk" which I need to provide to MAC of ethernet it gives following error on Vivado
[DRC REQP-1884] ODDR_has_invalid_load: ODDR cell sgclk_ddr_iob loads should only be an output buffer or a port, but it is driving an invalid load (one or more of):sgmii_clk_BUFG
How to use ODDR output inside sub modules without connecting it to output buffer or port?