How do I assign one of the outputs of a module to the output of a different module?

Question

module fullAdder(a, b, carryIn, carryOut, sum);
output carryOut, sum;
input a, b, carryIn;

wire w1, w2, w3, w4;


and G1(w1, a, carryIn);
and G2(w2, b, carryIn);
and G3(w3, a, b);
or G4(carryOut, w1, w2, w3);

xor G5(w4, a, b);
xor G6(sum, w4, carryIn);
endmodule

`timescale 1ns / 1ps

module oneBitALU(result, carryOut, a, b, carryIn, opCode);
output reg result;
output reg carryOut;
input a, b, carryIn;
input [3:0] opCode;
wire w1, w2, w3, w4, sum;


fullAdder add(a, b, carryIn, carryOut, result);
fullAdder sub(a, ~b, 1, carryOut, result);

always@ (opCode, a, b)
begin
case(opCode)
    4'b0000: assign result = a&b;
    4'b0001: assign result = a|b;
    //4'b0010: 
    //4'b0110: 
    4'b1100: assign result = ~a&~b;
endcase
end
    

endmodule

I'm trying to assign the sum value of the fullAdder module to the result value of the oneBitALU module. I'm pretty new to Verilog, so any help would be appreciated. Lines 19 and 20 of the oneBitALU module are where I would assign the value.

Answer 1

You can only have one source driving a given net, so having result being assigned in multiple places won't work (for synthesis at least). Furthermore the output a module cannot be connected directly to a reg type variable. Instead, to connect multiple things together in Verilog, you use wire (net data type).

For example

wire [3:0] addResult;

fullAdder add(..., addResult);

...

    4'b0010: result = addResult;

The same goes for carryOut. If you wrap all your cases in begin-end you can have multiple lines for each of the opCode cases, allowing you to assign both the result and carryOut variables during the case statement, again using intermediate wire data types to connect your fullAdder module outputs.

Furthermore, notice that inside the procedural always block, you don't need (and in pretty much all cases shouldn't) use the assign keyword. A simple = (blocking assignment) or <= (non blocking assignment) will do.