I am confused on a topic regarding NPN BJT transistors.
When there is a collector-emitter voltage (VCE) applied to the NPN transistor (as shown in the figure) without a emitter-base voltage (VBE), it is said that this forward biases the emitter-base junction (J1) and reverse biases the base-emitter junction (J2). My confusion arises when J1 is said to be forward biased, does this mean the depletion region at J1 is reducing in size since the collector is at a lower potential and electrons are entering the depletion region due to the negative terminal of the battery. When I think of forward biasing a PN junction, the depletion region reduces until it fully 'disappears' at 0.7V (for silicon). If the depletion region is slowly decreasing, doesn't this mean some electrons can enter into the P base region?
Apologies for the simple question, just slightly confused.
Edit: Where I have written 'it is said', I am referring to Fundamentals of Power Semiconductor Devices page 528 by Baliga.