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I believe such a question has been asked in the past but this is more comprehensive.

VHDL provides "external name" where we use an alias in a testbench to access signals that exist down the hierarchy in the DUT. SystemVerilog has a similar capability from what I am aware but I do not know if it has a specific name.

  1. Assume the scenario where the DUT is in VHDL and the testbench is in SystemVerilog, can the SystemVerilog access signals inside the VHDL DUT hierarchy?

  2. Assume the opposite scenario where the DUT is in SystemVerilog and the testbench is in VHDL, can the VHDL access signals inside the SystemVerilog DUT hierarchy?

As far as I am aware both the languages themselves do not permit this. It is possible that some simulator tools themselves have a support for such a feature but I do not know.

The solution that I can think of is that, we create a separate "wrapper component" in the same language as the DUT which will expose signals inside the hierarchy. We then just instantiate this in the testbench (which is created in the different language) and directly do a port map to this wrapper. The DUT will then exist inside this wrapper also. I cannot think of any other solution.

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Modelsim/Questa has a feature called "Signal Spy" which uses the underlying C programming interface to look up signals by a string name and access their values from one language to the other. I'm sure pother tools have similar features, but in any case this is not the most efficient way of accessing signals if there is going to be a lot of communication.

Verilog always had a hierarchical reference feature that VHDL recently added as external name in 2008. Hierarchical reference in Verilog can pass through Verilog/VHDL hierarchies and end in either language so long as the data types are compatible. External names in VHDL can pass though Verilog/VHDL hierarchies but must end in VHDL.

SystemVerilog has a bind construct that allows you to insert modules/interfaces deep inside the your SystemVerilog/VHDL DUT hierarchy. You can connect ports of these bound modules to the internal signals of your DUT and access them from your testbench.

See my DVCon paper The Missing Link: The Testbench to DUT Connection which shows how to use the bind construct to connect a SystemVerilog testbench to a SystemVerilog DUT, but it would work equally well with a VHDL DUT.

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  • \$\begingroup\$ So, Verilog has hierarchical reference that can actually access VHDL signals (std_logic_vector, std_logic, natural, integer, positive) in the VHDL DUT? But this is not possible with SystemVerilog? \$\endgroup\$
    – gyuunyuu
    Commented Feb 23, 2022 at 21:26
  • \$\begingroup\$ So SystemVerilog does not have hierarchical reference like Verilog but it has something called the bind construct? I will need an example of this. \$\endgroup\$
    – gyuunyuu
    Commented Feb 23, 2022 at 21:28
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    \$\begingroup\$ Anything Verilog has, SystemVerilog has too. The link I provided has an example of the bind construct. \$\endgroup\$
    – dave_59
    Commented Feb 23, 2022 at 23:00

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