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I would like to know the term that is used to describe the blueprints that are made by electrical engineers that describe in details how an IC is to be manufactured at a fabrication facility.

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You're asking about the layout of the integrated circuit. Here's an example screenshot, zoomed in, of a layout I did for my thesis:

enter image description here

This image was taken from a screenshot from one of my layout timelapse videos which shows how someone might go about creating such a layout at the CAD level. This is a zoomed-in detail view; a full layout for a chip will include the outer edge sealing ring, bond pads, and power supply interconnect, all of it made using similar geometry. Note that my chip is for analog use on a mixed-signal process. While it uses the same layers as e.g. a CPU would, the design methodology is different and the general geometric appearance of the circuits is likewise different.

You can take note of the different colors and patterns: Each represents a different layer of the design. For example, the light gray-blue represents polysilicon (gate or interconnect), red represents diffusion where the silicon is strongly doped, the light blue-green is the lowest metal layer, green are contacts from metal 1 to either poly or diffusion, and the yellow is the second metal layer. There are also layers that are harder to see here, which specify the type of doping, the thickness of the gate oxides, and so on.

The specific set of layers is a consequence of the specific silicon process you're working with; a 14 nm TSMC chip will have different layers than a 180 nm TSMC chip, which will itself have different layers than a 180 nm GlobalFoundries chip.

This geometric data can be stored in a design database in various formats such as GDSII. When I ordered my thesis chip from TSMC, I submitted a GDSII file to our intermediary who checked it and sent it to TSMC.

The layers are converted to physical Photomasks; a full set of masks for a chip is called mask work and is considered proprietary intellectual property.

The physical masks are actually used on the manufacturing floor. The wafers are coated with light-sensitive chemicals and loaded along with masks into a very precise and expensive optical projector known as a stepper; the masks are used to activate these light-sensitive chemicals in the desired pattern.

The masks roughly correspond to the layers that I showed above. For advanced processes with tight tolerances, the silicon foundry may perform tweaks (e.g. OPC). The final masks also include extra patterns, known as "dummies" which have negligible electrical effect on the circuit, but improve the yield of the manufacturing process.

Additionally, some masks correspond to the logical product of multiple layers. For example, the physical mask for P+ diffusions may be a logical 'AND' of the "diffusion" layer and the "P+ doping" layer, and the mask that's used to lightly dope MOSFET drains might be a logical function "diffusion AND not gate AND NOT mos_source".

As a bonus, here's a second view showing a full chip:

enter image description here

You can see bond pads, power rails, and the seal ring. The layers I mentioned before are mostly for features which are too small to see here; the visible layers are green (metal 9), white (metal 8), and red/white grids (MIM capacitor).

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  • \$\begingroup\$ Pardon my asking, you mentioned you did it for thesis and it was sent to TSMC. What kind of process was used and how much does it cost approximately, if you can reply? And who pays for manufacturing it? \$\endgroup\$
    – Ilya
    Feb 22, 2022 at 20:16
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    \$\begingroup\$ @Ilya I used TSMC 65nm 9-metal RF/Mixed-signal. My school paid, and it cost around $5000-6000 USD per square millimeter. The screenshot is actually from an earlier 180nm layout; the 65nm process is under a stricter NDA that makes me hesitant to take many screenshots (but it's similarly a planar process, rather than FinFET or DMOS) \$\endgroup\$
    – nanofarad
    Feb 22, 2022 at 20:17
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    \$\begingroup\$ @Ilya Here is a service that provides low-cost IC fabrication in the US, and the last time I used their services TSMC was one of the fabrication options: themosisservice.com \$\endgroup\$ Feb 22, 2022 at 20:52
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We call them “layout plots”, “mask plots”, or just “plots”. There is a separate plot generated for each layer mask that will be used in the production of the IC. On screen we look at the plots of one or more layers in a different color stacked on top of each other like you might in a PC board layout program. We don’t print them out much any more, but on paper we print one or more layers each of a different color onto the paper. This allows us to envision the differently layers of the IC and their interconnects.

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  • \$\begingroup\$ Sorry for the late comment. I did have a question to ask about the layout or plots as they are called. What are schematics then ? \$\endgroup\$
    – David J
    Mar 10, 2022 at 21:37
  • \$\begingroup\$ @DavidJ I just came across your comment much later, so apologies for the late response - schematics are a more abstract of the circuit that uses component symbols, lines, and labels. It's meant to be easily read and interpreted by humans rather than being an accurate scale drawing of where we need to place metal/dope silicon/grow oxides. I'll edit an example into my post later today when I'm at a desktop computer. \$\endgroup\$
    – nanofarad
    Apr 24, 2022 at 14:15

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