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I'm building a circuit to switch shunt resistors to keep the shunt voltage within 0~100mV. The idea is to measure current over a larger dynamic range while keeping the burden voltage low. It does this with two comparators which trigger the set/reset inputs of a latch. The latch outputs drive low-side FETs to add parallel resistance, and there are four stages of this beyond the initial shunt resistance - though I'm having trouble even when using only one.

The shunt voltage is amplified by 23 and compared against trim-pot-set voltages, 180mV and 2.3V for down-switching and up-switching respectively. The problem I'm running into is that with a rising current source from 0-115uA, after the first shunt switch, from 1kΩ to 100Ω, the voltage drops more than a factor of 10. It drops far enough to trigger the down-switching comparator, which switches the shunt from 100Ω to 1kΩ, which causes the voltage to rise, crosses the up-switch comparator, etc - and so we have oscillation

I've got an oscope capture at 115uA. I'd expect it to drop to 100uA x 100Ω x 23 = 265mV, but it drops lower than 180mV and causes oscillation.

115uA

  • CH1 (yellow): comp_down
  • CH2 (magenta): comp_up
  • CH3 (cyan): Vdut+Amp
  • CH4 (green): VSW0

Note that I've probed VSW1 and confirmed that it is NOT activating.

schematic

The microcontroller and FTDI chip are not populated, but the ENCAL signal is shorted to ground to work during these tests. I've also changed the capacitors on the low-pass filters to be 10nF instead of 1pF, as previously it was too fast and caused VSW1, VSW2, and VSW3 to basically mirror VSW0. The trim-pots are installed, not the fixed resistor divider. The LED and driver FETs are also not populated.

Some other miscellaneous info:

  • Powering with 5V off a bench supply. Noise doesn't look too bad
  • Current source is a 2n3906 with potentiometer to manually adjust, range is about 0 to 1.2mA
  • Board is a 4-layer PCB, internal layers are ground/5V

I know there's a lot of variables here, but I'm hoping somebody sees something simple I'm just missing. If it's just noise driving the signal into oscillation (doesn't look like it, but...) then I guess that's something I can try to manage. Thanks in advance!

Edit:

  • Fair point - I didn't consider how important it'd be to be close to 10x parallel per stage
  • I think I do though, don't I? I tried to design it such that if V>2.3, it switches up and if V<180mV, it switches down. I'd be happy to be wrong though, that sounds like an easy fix!
  • Not sure I understand this one. Looks like there's a good 10us between comp_up's pulse and comp_down's pulse.
  • Good point. I'll remove them for now. In my mind I saw more capacitance as more stable, but you're right they'll definitely induce a hard current draw
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You have no dead zone in your comparator setup, so when the sense voltage hits 2.3V it switches up, bringing the sensed voltage to 230mV, which switches back down. Even with the most precise shunt resistances (which you're a way off from) this is going to be wobbly.

There are additional issues, too. You're not accounting for the MOSFET's Rds(on), which means your shunt resistances get progressively further off spec - your lowest resistance shunt will come out at about 130mΩ. Your resistor values are also a little off anyway. All told they come out at 1k, 99.12Ω, 10.9Ω, 1.12Ω, and 0.13Ω, and that assumes that they're precision parts rather than 5% tolerance.

You haven't specified a value for C_small, but when each channel turns on that capacitor will charge and spike the load current for a moment. This is likely to cause a transient that might switch things back.

There's also the issue of switch-on time with the FET, and its parasitic capacitance. I'm guessing the switching is pretty quick with that driver, but there'll still be a moment when the FET isn't at its lowest Rds(on). There may also be a slight crossover period where two FETs are on.

My suggestions would be:

  • Recalculate your smaller shunt resistors to compensate for the 20mΩ Rds(on) of the FET.
  • Add some dead zone to your comparator setup so that there's some hysteresis between switching up and down.
  • Temporarily inhibit the action of comp_up and comp_down at switchover time, to provide additional protection against oscillation. A 2µs hold-off time should be fine.
  • Check your C_small value to make sure it isn't causing current spikes when the FETs switch on/off.
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  • \$\begingroup\$ Hey, thanks for taking the time to answer! Some responses / questions added to my question to maintain formatting \$\endgroup\$
    – Orotavia
    Feb 23, 2022 at 4:10

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