I'm trying to implement an synchronous 4-bit counter in Verilog on the DE10-Lite (according to the Intel Lab Exercise 4). The design works fine in simulation (counts from 0-15 repeatedly), but in hardware the loop skips 0 and 8. If I extend the counter to 5 bit, it skips 0, 8, 16, and 24. The pattern is repeatable and the switches are hardware-debounced. I added some input and output timing constraints, but no difference. I'm an FPGA novice, so this is probably something simple. Any help is appreciated. Thanks!

module DE10_LITE_Golden_Top(
  input              [1:0]      KEY,
  output             [9:0]      LEDR,
  input              [9:0]      SW);

  counter_4 c0 (.enable(SW[1]), .resetn(SW[0]), .clk(KEY[1]), .Q(LEDR[3:0]));
  assign LEDR[9:4] = {6{1'b0}};


// counter
module counter_4 (
  input        enable,
  input        clk,
  input        resetn,
  output [3:0] Q);

  wire [3:0]   T;

  assign T[0] = enable;
  tFlipFlop   c0 (.T(T[0]),   .clk(clk), .resetn(resetn), .Q(Q[0]));
  assign T[1] = Q[0] & T[0];
  tFlipFlop   c1 (.T(T[1]),   .clk(clk), .resetn(resetn), .Q(Q[1]));
  assign T[2] = Q[1] & T[1];
  tFlipFlop   c2 (.T(T[2]),   .clk(clk), .resetn(resetn), .Q(Q[2]));
  assign T[3] = Q[2] & T[2];
  tFlipFlop   c3 (.T(T[3]),   .clk(clk), .resetn(resetn), .Q(Q[3]));


//  t Flip-flop
module tFlipFlop (
  input       T,
  input       clk,
  input       resetn,
  output reg  Q);

  always @(posedge clk) begin
       Q <= 0;
      if (T) Q <= ~Q; 


Edit: Note that I am using the button input as a "clock", there is no other clock involved.

  • \$\begingroup\$ Classic debouncing problem. Add a debouncer module to filter button input. Something like this: chipmunklogic.com/digital-logic-design/… \$\endgroup\$
    – Mitu Raj
    Feb 24, 2022 at 15:27
  • \$\begingroup\$ @MituRaj, how would a 'classic debouncing problem' explain the stops at precise counts that the OP has, though? \$\endgroup\$
    – TonyM
    Feb 24, 2022 at 17:09
  • \$\begingroup\$ Please can you edit your question and add a link to the Intel Counter Tutorial you mention. Without that, we can't know if you've implemented the right circuit in the right way. \$\endgroup\$
    – TonyM
    Feb 24, 2022 at 20:32
  • \$\begingroup\$ Thank you all! I implemented a debouncer circuit, similar to the fpga4fun debouncer and this seemed to have done the trick! The counter works now. But for my own education, can someone explain why the (wrong) pattern before was very repeatable? Why did the previous circuit (only the HW debounce and Schmitt trig) always skip the same counts? I also provided the link to the tutorial as an edit. \$\endgroup\$
    – physguy
    Feb 25, 2022 at 2:37
  • \$\begingroup\$ The fpga4fun debouncer is a clock domain crossing circuit though, not a switch debouncer. Looks like the hardware RC debouncer is sufficient. Is the Schmitt trigger input enabled on the MAX 10? They're not by default, check your .QSF \$\endgroup\$
    – TonyM
    Feb 26, 2022 at 17:42

2 Answers 2


Not trying to diagnose your problem but just looking at the weaknesses of your circuit...

  • Don't rely on external hardware debouncing, which for a demo' board is almost certainly just a parallel capacitor. Add a debouncing circuit to your Verilog firmware. There's plenty of explanations and example Verilog on switch debouncing already available through an internet search.

  • Your switches change asynchronously to the logic clock, so your circuit can go metastable. You should filter the switch inputs. Don't just put them through two D-type Flip-Flops - that'll bring them into the clock domain but not reject switching noise. A decent debouncing circuit will provide this noise filtering.

  • The hardware RC debouncing will produce a slowly-changing signal from the switches when either pressed or released. Ensure that your FPGA's input pins from the switches have Schmitt triggers enabled.

  • Your T-type Flip-Flops (TFFs) are toggled on every clock that the switch is pressed for, so the counter will be running fast. I know your question says you don't see this but its still a weakness of the circuit.

If you fix these, you will see new behaviour for your circuit that may or may not have solved your problem. But you will be proceeding from a stable starting point.

  • \$\begingroup\$ Thanks for the tips! I'll try the extra debounce circuit tonight. In the meantime, I don't use an actual clock - the button input is my clock. I know this is not the usual way a clock is used, but that was the way the tutorial was set up. Also, the board has a hardware debounce circuit (unspecified) in addition to the Schmitt trigger input of the MAX10. The pattern is very repeatable (but wrong), so I figured it's something in my code that's off. \$\endgroup\$
    – physguy
    Feb 24, 2022 at 12:49

It may be something to do with the "clock" signal from your button not arriving to every flop at the same time. There are constraints for clock routing, but I think putting the button input through a synchronizer (usually a 2 or 3 bit serial in-serial out shift register clocked with the system clock) would help, not to synchronize it (since you don't have another clock in your design), but to give the signal a sharp edge. https://www.fpga4fun.com/CrossClockDomain1.html

  • \$\begingroup\$ To be fair, he does have two "clocks": the system clock and the button clock. I am surprised that without synchronization the pattern is repeatable - I would expect setup/hold times to fail randomly as the button edge is asynchronous. \$\endgroup\$ Feb 23, 2022 at 8:11
  • \$\begingroup\$ Thanks! I actually use only the button as a "clock", so there is no other (system) clock (as far as I know). I was also suspecting a timing issue, but curiously, it is the first flop (bit 0) that acts up, which has no other signal going to it other than my button. I'll try the "synchronizer" tip tonight! \$\endgroup\$
    – physguy
    Feb 24, 2022 at 12:57

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge that you have read and understand our privacy policy and code of conduct.

Not the answer you're looking for? Browse other questions tagged or ask your own question.