Where do the procedural block, fork - join, and specify-endspecify block lie in the Verilog timing region? Rough guess is Active or NBA region.
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The region of execution for most statements depends solely on where the process that initiated it is located, not the statement itself. The initial,always, or continuous assign statements are constructs that initiate processes. If those constructs are located in a module or interface, then the process executes in the the active region. If those constructs are located in a program (which I do not recommend ever using), the the process is executed in the re-active region.
Some procedural statements execute in one region, but schedule events in another. A nonblocking assignment evaluates the RHS as I just described above, but schedules the update of the LHS in the NBA or re-NBA region. The statements in the action block of a concurrent assertion always executes in the reactive region.
To answer your specific question about begin/end, fork/join, it should should now be clear that it only matters how the process got started where these procedural blocks are executed. A specify block is not a procedural block.
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\$\begingroup\$ If I understand correctly, the procedural keywords like begin/end or fork/join don't produce any output by themselves, it is the statement(s) inside these which are doing some operation which requires event scheduling. So, if I were to assume Verilog code written in module level construct (not a program block), these proc blocks and specify block should fall in the active region, right? If you could share some info about how to better understand Verilog NBA, it would awesome. Your answer on Vivado HDL debugging was enlightening, very helpful and helped build fundamental understanding. \$\endgroup\$ Feb 23, 2022 at 18:49
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1\$\begingroup\$ As I said in my Answer, it does not matter where the statement are written, but where the process got started. You could have an initial block in a program that calls a task in a module. The statements inside the task written in a module will execute in the re-active region. You would make learning about SystemVerilog much easier if you just forget about program blocks. There are already many posts about the semitics of Verilog NBAs \$\endgroup\$– dave_59Feb 23, 2022 at 22:00
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\$\begingroup\$ Now it makes more sense to me what you were saying earlier! Thank you! \$\endgroup\$ Feb 24, 2022 at 5:23
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The execution of Verilog statements depends on what statements are executed rather than where they are executed from. Blocking assignments, non blocking, assignments, $display, and $monitor/$strobe are treated differently.
This paper:
http://www.sunburst-design.com/papers/CummingsSNUG2006Boston_SystemVerilog_Events.pdf
does a nice job explaining the Verilog & SystemVerilog stratified event scheduler.
Here is figure 1 from that paper.
SystemVerilog is more complex than Verilog as explained in the paper. In SystemVerilog, statements executed from program blocks behave differently. The paper also explains the details of code executing from a SystemVerilog program block.
