I am trying to use the Radio 4 198kHz carrier frequency to discipline a PLL, in order to generate a pulse-per-second (PPS) output that is stable over several hours.
The issue I am facing is that the PLL slips. Every few seconds it locks on to the wrong edge, causing the output to slow and the PPS to drift by 1 cycle (around 5us).
The Radio 4 broadcast encodes data by adjusting the phase of the carrier by 22.5°, up to 50 times per second. It is supposed to average out over 1 second so that when used as a frequency reference, long term stability is ensured.
My schematic for the PLL looks like this:
The input to the PLL is the output from the amplified 198kHz carrier and a comparator that converts it to a square wave. Of course, the carrier has noise.
The prototype is on breadboard. I have tried adjusting the low pass filter capacitor C33. 1n seems to be less prone slipping than 100n as shown in the schematic, but it does not eliminate it. It also tried chaining a second 4046 to the 1.98MHz output, in exactly the same configuration except that the 4026 is removed from the loop so that it outputs 1.98MHz too. That actually produced worse output.
I am checking the PPS output against a GPS receiver. The goal is to keep the PPS within 1us of UTC for at least an hour, using the 198kHz carrier as a reference. The carrier is disciplined by atomic clocks at the transmitter.
How can I prevent the slipping?