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I am trying to use the Radio 4 198kHz carrier frequency to discipline a PLL, in order to generate a pulse-per-second (PPS) output that is stable over several hours.

The issue I am facing is that the PLL slips. Every few seconds it locks on to the wrong edge, causing the output to slow and the PPS to drift by 1 cycle (around 5us).

The Radio 4 broadcast encodes data by adjusting the phase of the carrier by 22.5°, up to 50 times per second. It is supposed to average out over 1 second so that when used as a frequency reference, long term stability is ensured.

My schematic for the PLL looks like this:

The input to the PLL is the output from the amplified 198kHz carrier and a comparator that converts it to a square wave. Of course, the carrier has noise.

The prototype is on breadboard. I have tried adjusting the low pass filter capacitor C33. 1n seems to be less prone slipping than 100n as shown in the schematic, but it does not eliminate it. It also tried chaining a second 4046 to the 1.98MHz output, in exactly the same configuration except that the 4026 is removed from the loop so that it outputs 1.98MHz too. That actually produced worse output.

I am checking the PPS output against a GPS receiver. The goal is to keep the PPS within 1us of UTC for at least an hour, using the 198kHz carrier as a reference. The carrier is disciplined by atomic clocks at the transmitter.

How can I prevent the slipping?

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  • \$\begingroup\$ What are the specs of capacitor C33? How happy is the 4046 on 3V? Might it work better on 5V? \$\endgroup\$
    – Kartman
    Commented Feb 23, 2022 at 10:52
  • \$\begingroup\$ C33 is a ceramic disc from a selection box. I measured the ones I tried at 110nF and 1.2nF. \$\endgroup\$
    – user
    Commented Feb 23, 2022 at 10:59
  • \$\begingroup\$ The CD74HC4046 should be fine at 3.3V. However, I'm wondering about the CD4026B -- it's only guaranteed to work up to 2.5 MHz @ 5 V, and the "typical" curve drops steeply in that range of voltages. It could very well be that it can't quite keep up at 1.98 MHz and 3.3 V. I would recommend switching to a 74HC device for your counter, too. (Or raising the supply voltage to 5 V.) \$\endgroup\$
    – Dave Tweed
    Commented Feb 23, 2022 at 12:19
  • \$\begingroup\$ @DaveTweed The 4026 is struggling. I have to manually reset it whenever I power cycle the circuit. I have ordered a 4024 to replace it. \$\endgroup\$
    – user
    Commented Feb 23, 2022 at 14:10

1 Answer 1

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You need to narrow the loop bandwidth of the PLL. I haven't worked through your design, but the compensating zero (R16 and C33) has a frequency of 723Hz, suggesting your loop bandwidth is at least 1500Hz. If you want to average out these phase transitions you need a much lower bandwidth, then the output phase is effectively averaged over many more transitions.

You need to work out your VCO Kv and the transfer function of the loop filter to compute the loop bandwidth. Reduce it to a few hundred Hz (or less) and see if the problem persists.

Here's a TI 4046 application note that might help:

www.ti.com/lit/an/scha003b/scha003b.pdf

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  • \$\begingroup\$ Thanks. Looking at that app note, it looks like example 3 and 4 on page 37 are the ones I need to work through. \$\endgroup\$
    – user
    Commented Feb 23, 2022 at 11:01
  • \$\begingroup\$ The best simple-language explanation of the CD4046 I have read is in Don Lancaster's CMOS Cookbook , IBSN 81-7029-795-8, which discusses the pitfalls of using this device. \$\endgroup\$
    – user131342
    Commented Feb 23, 2022 at 11:19
  • \$\begingroup\$ It's only been going for half an hour but I have used a simple RC LPF at 0.7Hz and it's been stable so far. Thanks for this hint. \$\endgroup\$
    – user
    Commented Feb 23, 2022 at 15:00
  • \$\begingroup\$ So it's nearly perfect but never runs for much more than an hour without slipping. I have tried as low as 0.16Hz with little improvement. At 0.03Hz it actually gets worse, and at 0.01Hz it can't lock. \$\endgroup\$
    – user
    Commented Feb 24, 2022 at 13:39
  • \$\begingroup\$ You are probably running into the stability limit of the RC oscillator itself. I would have tried to lock a crystal osc, or at least an LC osc, but as it seems to sort of work you may be able to improve it. All I can suggest is to make sure that the power supply is very clean, perhaps try running it on batteries. \$\endgroup\$
    – Tesla23
    Commented Feb 24, 2022 at 22:50

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