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VHDL has a clear distinction between signals and variables. Variables are always updated as soon as we assign a value to them. However, a signal is only updated at the end of the process block.

In Verilog and SystemVerilog there is no distinction like variable and signal found in the VHDL. However, here we have the concept of blocking and non-blocking assignment. The non-blocking assignment behaves like the variable in VHDL while the blocking assignment behaves like the signal in VHDL. Atleast this is my conclusion.

Now the issue is that, it is allowed to mix blocking and non-blocking assignment for the same reg or logic type in Verilog/SystemVerilog. This brings me to my question (about synthesizeable code):

  1. I assume that mixing blocking and non-blocking assignments for synthesis code for the same reg or logic type, is a bad idea. Why is it allowed in the language?
  2. How does one make sure that mixing of blocking and non-blocking assignment for the same reg or logic type does not happen (by mistake)?
  3. Is it a good practice to have blocks of code that combine reg or logic types like we can have signal and variable in the same VHDL process?

Note: This question is not asking about difference between the blocking and non-blocking assignments

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  • \$\begingroup\$ How does one make sure that mixing of blocking and non-blocking assignment for the same reg or logic type does not happen (by mistake)?" -- A good designer doesn't mix it. As simple as that. However linting tools can catch this, not sure about RTL compilers or synthesisers. \$\endgroup\$
    – Mitu Raj
    Commented Feb 25, 2022 at 18:00
  • \$\begingroup\$ A good designer may not mix them on purpose, its just = vs <=, very easy to mix up if a code block is using both of them anyway \$\endgroup\$
    – quantum231
    Commented Feb 25, 2022 at 18:38

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I assume that mixing blocking and non-blocking assignments for synthesis code for the same reg or logic type, is a bad idea. Why is it allowed in the language?

Verilog and SystemVerilog can also be used for simulation and it currently supports way more than what can be synthesized. And mixing them in simulations works ok.

How does one make sure that mixing of blocking and non-blocking assignment for the same reg or logic type does not happen (by mistake)?

You will get a synthesis error if you do that, so eventually you will stop doing it. Also, the syntax is quite different = vs <=

Is it a good practice to have blocks of code that combine reg or logic types like we can have signal and variable in the same VHDL process?

As far as I know reg can always be replaced by logic in SystemVerilog. In fact, you will only not use logic (and explicitly specify that the variable is a reg or wire) when you have multiple drivers for a net, then you should use wire and deal with the multiple drivers explicitly.

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  • \$\begingroup\$ The last sentence does not make sense "In fact, you will only not use logic when you have multiple drivers for a net, then you should use wire." \$\endgroup\$
    – quantum231
    Commented Feb 24, 2022 at 10:56
  • \$\begingroup\$ I updated that phrase, also here are some other resources stackoverflow.com/questions/13282066/… electronics.stackexchange.com/questions/331393/… . logic was introduced only in SV while reg and wire already existed in Verilog. I don't know any situation where a reg type cannot be changed to logic, almost the same holds for wire, except that logic cannot be driven by multiple drivers, for that you have to explicitly declare it as wire \$\endgroup\$
    – jDAQ
    Commented Feb 24, 2022 at 15:41

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