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The SystemVerilog logic type can take one of these possible values per bit: '0', '1', 'X' and 'Z'.

The VHDL std_logic type can take one of these values per bit: '0', '1', 'X', 'Z', along with 'U', 'W', 'L', 'H' and '-'.

I am a user of VHDL and am trying to learn SystemVerilog. I am totally confused that SystemVerilog logic type and the VHDL std_logic types are different in this way. This raises a few questions for me:

  1. Why were Verilog and SystemVerilog logic type not made as versatile as VHDL? I am sure this will have some type of drawbacks in certain use cases.
  2. In VHDL simulation it is common to have values 'U' and sometimes (only for top level ports) 'L' and 'H'. How are these supposed to be handled in a SystemVerilog design by the simulator?
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  • \$\begingroup\$ The VHDL types are like that because that's an IEEE standard, IEEE 1194. I don't know enough about Verilog to know whether it also implements the standard. \$\endgroup\$
    – Hearth
    Commented Feb 25, 2022 at 18:36

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Actually it is the other way around. For nets, SystemVerilog has 8 different "1" strength states and 8 "0" strength states, plus certain combinations of these strength/state combinations. This is needed to handle switch level transistor modeling, something that VHDL does not do. In both languages, strength is used to resolve multiple drivers on a net(Verilog)/signal(VHDL). Variables cannot have multiple drivers. In Verilog, strength gets associated with the driving statement or gate primitive and distinct from the data type value 0,1,X, or Z.

Strength name level
supply 7
strong 6
pull 5
large 4
weak 3
medium 2
small 1
highz 0
VHDL state Verilog strength/state combination
U Not translatable
X strong0/strong1
0 strong0
1 strong1
W weak1/weak0
L weak0/highz0
H weak1/highz1
Z highz1/highz0
- Represented by literal X
Ambiguous Strength not translatable pull1/weak1 strong0/pull0
Ambiguous Strength/State not translatable pull1/weak0 strong1/small0
VSS not translatable supply1
VDD not translatable supply0

The only thing missing is the VHDL 'U' state. I would suggest looking at static formal verification instead of relying on dynamic simulation and this 'U' state. Dynamic simulation relies on a specific set of stimulus and does not take consider reconvergence (i.e. An uninitialized counter will eventually reset, or subtracting a register from itself). Formal tools can exhaustively prove an Uninitialized variable will eventually or never become initialized.

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  • \$\begingroup\$ What do you mean by "static formal verification"? \$\endgroup\$
    – quantum231
    Commented Feb 24, 2022 at 10:54
  • \$\begingroup\$ Also, you imply that while logic type in SystemVerilog can have only 4 possible states, this is not the case with the nets. But there is no net type in SystemVerilog, we only have logic, reg and wire, right? \$\endgroup\$
    – quantum231
    Commented Feb 24, 2022 at 10:55
  • \$\begingroup\$ Logic equivalence checking tools for example (more ASIC than FPGA processes though). In software, SPARK applied to Ada is a good example. Formal proof is always more complete than testing, where it is possible. "U" in VHDL is great; you don't need to analyse the nature of the problem; you already know one or more inputs are uninitialised, it's just a matter of looking at those inputs to see which. \$\endgroup\$
    – user16324
    Commented Feb 24, 2022 at 13:29
  • \$\begingroup\$ @quantum231, reg and logic are data types. then there are variables and nets which can have those data types. I've updated my answer with other clarifications. Also see blogs.sw.siemens.com/verificationhorizons/2013/05/03/… \$\endgroup\$
    – dave_59
    Commented Feb 24, 2022 at 17:46

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