How can I make a hexadecimal 7-segment display driver immune to intermediary states using basic logic gates (where each gate has a 1hz refresh rate)?
The problem I'm running into is that on the first two cycles after the input transitions from, say, 0100 to 1000, the display temporarily shows some garbage states before it finally shows 8.
This seems to be due to a combination of two factors:
- Certain segments update quicker than others, due to the 7-segment driver having a different number of gates the change must propagate through before reaching each segment. Since each gate takes one cycle to react to a change of input, some changes take longer to propagate.
- The ALU, an exact replica of a 74181, exhibits similar intermediary garbage states after changes in input, probably for a similar reason.
I once read that one of Steve Wozniak's first tasks at HP was to solve this exact problem so their calculator's display would not show garbage states between updates. However I'm no Steve Wozniak so I'm coming to you for help.
Does anyone know of a circuit diagram of a solution to this problem?
The only gates I can work with are:
- INVERTER (inverts the input value, responds to change after 1 cycle)
- AUTO-SWITCH (passes thru the input value, responds to change after 1 cycle)
AND and OR gates can be formed of serial or parallel AUTO-SWITCHES; NOT and NOR can be formed of serial or parallel INVERTERs. AND/OR and NOT/NOR both update their final value after one cycle assuming all input changes are simultaneous. With XOR etc. it gets a bit more complex, so these circuits are typically slower (could explain the wonkiness in my ALU):
One solution I'm considering would be to introduce delays where needed, but I'm not sure where to find a good guide on how to formalize this problem (I have my truth tables but they don't account for certain paths taking longer than others through the logic).
Another possible solution would be to somehow make a time gate that waits 3 seconds after the first update to check for new values to display. This would seem to require also building some kind of RAM out of these two basic gates, though, and I'm not sure the best way to attempt that.
I wonder if you might have any additional advice or recommendations?
Disclaimer: this is not from homework. I'm just a professional software engineer tinkering with logic gates in the video game, No Man's Sky, but it's the same problem as if the circuits were real.
I can add screenshots of the existing circuits if that would help, but mainly I'm just curious if anyone is aware of an existung circuit design since I'm sure this problem has already been solved many times over the past 50 years.
