In my little time studying digital systems, it seems that textbooks immediately jump to the fact that we implement adders via serial (i.e. the chaining together of) full adders. It's not a priori clear to me why we do this. In particular, since this is still a combinational circuit, why can't we write out the truth table (obviously, for large numbers we'd let CAD systems do this) and derive an optimized set of logic functions for each sum bit and the final carry out bit? Is this intractable? Is this equivalent to the serial full adder implementation? Any references discussing why we don't do this would be greatly appreciated!
EDIT to the above: I am familiar with lookahead adders and the like. The fact remains that these "begin" with chaining together one-bit adders, admittedly with some slick optimizations. Again, it's not a priori clear to me why we don't implement the "full" n-bit adder with combinational logic optimization techniques.