Why do we implement adders via serial full adders as opposed to an optimized logic circuit?

Question

In my little time studying digital systems, it seems that textbooks immediately jump to the fact that we implement adders via serial (i.e. the chaining together of) full adders. It's not a priori clear to me why we do this. In particular, since this is still a combinational circuit, why can't we write out the truth table (obviously, for large numbers we'd let CAD systems do this) and derive an optimized set of logic functions for each sum bit and the final carry out bit? Is this intractable? Is this equivalent to the serial full adder implementation? Any references discussing why we don't do this would be greatly appreciated!

EDIT to the above: I am familiar with lookahead adders and the like. The fact remains that these "begin" with chaining together one-bit adders, admittedly with some slick optimizations. Again, it's not a priori clear to me why we don't implement the "full" n-bit adder with combinational logic optimization techniques.

Answer 1

For the smallest circuit, the truth table would be best satisfied by the chain of full adders with ripple carry.

Or it could be done by a look-up table (a ROM), which would use vastly more gates and therefore either be slower or a waste of gates or both, for nearly all adder applications. The latter is weighing up the huge number of small counters in logic designs as well as the fewer large CPU ALU adders.

Answer 2

For volume production the one bit full adder is implemented in silicon as a highly optimised cell, optimised for speed and silicon area).

It is usually better in terms of silicon area to use this optimised cell for multiple adders rather than breaking down the adders into their resulting logic functions, which get very complex very quickly, and then implementing them as gates that do not have this optimisation.

Answer 3

Adder structure is inherently sequential because of the carry propagation. Think about how we add numbers together. If you have 1001 + 9999, you’ll need to wait for the carry to propagate all the way through from the least significant digits to the most significant digit.

All the look ahead adders are attempting to shorten the carry propagation delay by adding more gates. For example, the Kogge-Stone Adder has logarithmic carry propagation delay instead of the linear delay of a ripple adder.

In fact, this is a big problem when fast counters are required. When you have a large pipeline that runs as fast as the technology would allow you need to count the number of cycles until it is filled. However, a counter comprising an adder cannot propagate as fast. To avoid this we use linear-feedback shift registers. Instead of counting from 0 to 99, they produce a seemingly random sequence of length 100, e.g. 256, 147, 5 etc. However, the propagation delay is one logic gate.