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I was trying to understand the meaning of various specs given in a typical ADC datasheet, and I came across this article. Now, if I understand correctly, it seems to me that the accuracy of the ADC in bits can be taken as \$n - \log_2{{e}}\$ bits, where \$n\$ is the number of output bits of the device (its resolution?) and \$e\$ is the INL (integral non-linearity) error in terms of LSB.

My questions are:

  1. Is my understanding correct? If not, what is the correct explanation?
  2. If a 16-bit ADC has a INL of \$\pm 4\$ LSB, can we say that the accuracy of the ADC is 14-bit, and will have to ignore the lowest 2 bits for most practical purposes?
  3. Here is a 16-bit ADC with a typical INL of \$\pm 0.4\$ LSB. Does this mean the device has a typical accuracy of more than 17-bits? How is this possible? Or does it mean the device typically has an accuracy of over 17 bits, but since it has only 16 output bits, it has to truncate the data to a lower resolution?
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  1. Sort of ... if you look further down the page in the linked article, you'll a good explanation of the gain and offset errors. Particularly fig.5 So if you only have gain errors sometime the digital range is suppressed and in some cases the analog input range is suppressed. The former case is explained by your formulae. The later not. You need to account for gain differences.

  2. That would be one way, however, if it's the analog that is suppressed AND you have sufficient noise in the sampled signal to hide your computational noise you could conceivably be able to post multiply to get your full 16 bit range (span) back. Because of the noise present you won't have a full resolution ADC (ENOB - Effective Number of Bits). If you don't have enough noise then you'll notice this fractional multiplication. You don't mention your application but in images this wouldn't be acceptable.

  3. It just means that the INL is low, it doesn't speak to having to truncate the length because that is limited by other factors like DNL. What is does mean is that architecture (circuit technique) has promise for further extension to 17 bits.

Other factors do come into play in your decision. Monotonicity is one. A non-monotonic ADC will have high INL and NOT be correctable.

The article is good, but it does say some things that are applicable to certain architectures of ADC. One statement is " a LOW INL means a low DNL" to paraphrase the very first sentence in the INL section is not necessarily true in all cases.

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  • \$\begingroup\$ Thank you! A follow-up question regarding point 2: I did not understand how sufficient noise in the signal can help get back the 16 bits? \$\endgroup\$ – mayank Mar 16 '13 at 19:46
  • \$\begingroup\$ That wasn't clearly stated, corrected answer. \$\endgroup\$ – placeholder Mar 16 '13 at 19:50

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