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I'm new to the 555 timer and I'm trying to understand the configuration shown in the image below.

555 Timer with 50% duty cycle

The tutorial mentions that the capacitor C1 now charges and discharges through the resistor R2. The charging part makes sense to me because if the voltage at the output is high, then the charging current flows through R2 and the capacitor charges.

However, when the output is low and the capacitor discharges, wouldn't the voltage that gets sent from the capacitor through the R2 resistor change the output voltage? What is going on here? where would the voltage of the capacitor go without changing the output voltage?

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3 Answers 3

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Other Answer is also correct.

Not all designs on the web are great designs, including this site.

This example you show is another one not so great because the internal resistance is not shown that is controlled by the feedback to trigger. This is why the open collector trigger may be better to reset the analog voltage and enable the rise to trigger threshold.

Here is my "internals simulation" that allows you to speed up or stop and change any connection and press reset or undo last change. (^Z)

I've shown both Discharge and Output feedback connections so you can see the difference in results when you change resistor levels with mouse wheel.

enter image description here

The datasheet shows a more detailed internal schematic which has the same results as the simulator.

enter image description here

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  • \$\begingroup\$ I think I understand this more. So when the capacitor begins to discharge, the simulation showed that the current flows through the base of the BJT and it re-directs it to the ground allowing it to discharge without the output signal changing \$\endgroup\$
    – miiguell
    Mar 2 at 17:11
  • \$\begingroup\$ It's more that the two op-amps create a range for the output. Exceed the range, discharge. \$\endgroup\$ Mar 3 at 14:51
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The output voltage is "stiff", it won't change much as a result of loading via any reasonable value of R2 (say in the K ohms or more). Without R1 the capacitor simply charges and discharges through R2, with close to 50% duty cycle (very close for a CMOS 555).

When the capacitor is charging, R1 and R2 are essentially in parallel so the time constant (not quite the time, since it charges from 1/3 Vcc to 2/3 Vcc, which takes about 0.7\$\tau\$) is just \$\tau = C\cdot\frac { R_1 \cdot R_2}{R_1+R_2} \$

Now when the capacitor is discharging we have a different situation. The resistors are still effectively in parallel so we have the same time constant- however it not discharging towards GND but rather towards \$V_{CC} \cdot\frac {R_2}{R_1+R_2}\$. So if R2 is greater than 50K the capacitor voltage can never reach the lower threshold of Vcc/3. In fact it should be a fair bit lower to have stable operation. The time to discharge from 2/3 Vcc to 1/3 Vcc (ideally, assuming the output switches from 0V to Vcc and has no internal resistance) is just

t(low) = \$C\cdot \frac { R_1 \cdot R_2}{R_1+R_2} \ln(\frac{2R_1-R_2}{R_1 - 2R_2}) \$ (valid for R2 < R1/2) .

The purpose of R1 in this circuit is probably to slightly extend the 'low' time to compensate for the output of the bipolar version of the 555 which does not swing all that close to Vcc, in order to get closer to 50% duty cycle (which the CMOS version of the 555 does quite well without R1 when lightly loaded). The proper value will depend on the supply voltage and other factors (as well as R2, of course), but it should always be much greater than double R2.

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tl;dr: for reasonable values of R and C, both OUT and DISCH have enough drive capability to handle discharging / charging the capacitor.

Normally, you’ll see 555 astables use the DISCH pin, and an external resistor pulls up that pin to charge the capacitor. This is because the discharge pin is open collector with no high drive of its own.

When the OUT pin is used instead to achieve 50% duty, it has its own high drive so it doesn’t need a pull up resistor. So the capacitor charges up through R2.

R2 has to be a high enough value, or C2 small enough that the charge/discharge current does not overwhelm the OUT pin drive capability.

(Ed. Note: R1 isn’t necessary.)

Here is a simulation of the 555, showing its internals in the ‘typical’ astable configuration using DISCH (simulate it here):

enter image description here

This astable relies on the pull-up resistor to charge the capacitor. It isn't capable of 50% duty cycle because the charge and discharge resistances aren't equal: charge is 11k, discharge is 10k when DISCH grounds the pull-up.

We can fix this by reconnecting the 10k resistor directly to OUT (simulate it here):

enter image description here

Here, charge and discharge are both through the 10k to OUT. The the charge/discharge currents are equal, so the duty is 50%. Yet the current is small enough (0.33mA max) that OUT can handle it without losing its state.

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  • \$\begingroup\$ I think I understand this more. So when the capacitor begins to discharge, the simulation showed that the current flows through the base of the BJT and it re-directs it to ground allowing it to discharge without the output signal changing \$\endgroup\$
    – miiguell
    Mar 2 at 17:11
  • \$\begingroup\$ In the first sim, the DISCH current goes to the NPN collector, not the base. But the point is, for reasonable R and C, both the DISCH and OUT pins have enough drive capability to handle charging and discharging the capacitor. \$\endgroup\$ Mar 2 at 17:56

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