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I have a display sample that I'd like to interface with a Linux SBC, the only issue is that the connector is not compatible. To make it possible to interface the two parts I've designed a PCB, trying to follow guidance on differential pair routing I found in a TI document.

My layout is below. It's a 4 layer PCB with two internal ground planes. I've used 7 mil trace width with 5 mil spacing, top and bottom layers (35um copper) are 0.2mm from the ground plane below. With all these things taken into account I believe I have a 90ohm differential impedance.

The overall distance between the two connectors is about 800mils. Unfortuantely I was unable to avoid vias due to the connector pin layout.

This is my first multi-differential pair layout, so I could really use some feedback. Is this design sufficient to work for MIPI DSI?

enter image description here

enter image description here

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  • \$\begingroup\$ Not familiar with the interface you're talking about. Can you provide some of the major requirements such as diff Z tolerance, length matching, etc. Also a link to a reference for that interface would be helpful. \$\endgroup\$
    – SteveSh
    Commented Mar 3, 2022 at 13:26
  • \$\begingroup\$ Annoyingly the MIPI DSI standard is one that's only available under license, but I found this page that has some relevant detail: pcbartists.com/design/pcb-design/mipi-dsi-pcb-layout-notes \$\endgroup\$
    – Sensors
    Commented Mar 3, 2022 at 14:05
  • \$\begingroup\$ The traces to R12 and R13 seem to cross over themselves twice \$\endgroup\$ Commented Mar 3, 2022 at 14:40
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    \$\begingroup\$ If you use two ground planes, I'd consider adding stitching vias where the pairs cross layers (top/bottom). \$\endgroup\$
    – Wesley Lee
    Commented Mar 3, 2022 at 14:46
  • \$\begingroup\$ @Damien - maybe for length matching within the diff pair? \$\endgroup\$
    – SteveSh
    Commented Mar 3, 2022 at 15:31

3 Answers 3

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It's a 4 layer PCB with two internal ground planes.

It's not a rule but generally, the outer layers are kept for signal lines and the internal layers are kept for power lines, one for positive (VCC, VDD or whatever) and the other one for GND. Using two GND layers on top of each other can make the impedance control a bit more complicated Someone please correct me if I'm wrong.

I've used 7 mil trace width with 5 mil spacing, top and bottom layers (35um copper) are 0.2mm from the ground plane below. With all these things taken into account I believe I have a 90ohm differential impedance.

The differential impedance of MIPI tracks should be 100 Ohms, not 90 (USB requires 90). Using this calculator, I found 100 Ohms by giving 9 mils of track width, 5 mils of track separation, 8 mils of dielectric (prepregs usually have a dielectric constant of 3.5 to 4.5 and I took 3.5) and 1.4mils/35um of copper thickness. Remember that you can't hit 100.0 Ohms in practice so I personally give a 5% tolerance.

And also, it's always good to have each pair the same length.

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  • \$\begingroup\$ Thanks, didn't realise it was 100 Ohms. I'm using a 4L impedance controlled stackup with a 7628 dielectric prepreg, which has a constant of 4.6 (cart.jlcpcb.com/impedance). I'll adjust for the higher impedance though and add some length to the shortest trace. It's not a huge distance so hopefully the mismatch will be <1mm. \$\endgroup\$
    – Sensors
    Commented Mar 4, 2022 at 8:38
  • \$\begingroup\$ @Sensors yeah, 7628s have a dielectric constant of 4.5. I was thinking about using 2116s as they are thinner thus easier to adjust the required thickness. Another option is 106 which is even more thinner. These two have a dielectric constant of approx. 3.5. \$\endgroup\$ Commented Mar 4, 2022 at 8:48
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Because you are changing layers (vias) you need to allow the return path to follow the differential signal. While particularly true for single ended signals, no differential pair is perfect so there will always be a return path. Add ground vias close to the layer transition vias of the differential pairs. For high speed signals, the return path will always follow the path of least inductance. This will be as close as possible to the driven signal line. In this case, in the ground plane directly under the driven signal. Once the signal transitions to another layer so must the return path transition to the ground plane nearest the driven signal. Not doing so will degrade signal integrity.

There are numerous references on this. Howard Johnson is a notable author on the subject.

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Yes you could use that stackup Signal/GND/GND/signal. Actually it's the best 4 layer Stackup that allow you to change layer and keep the same reference plan when you do the routing, as well it's good for EMI because of good decoupling between the power on the Top or bottom layer and the GND layers as the thickness between THE Top layer and GND or the Bottom layer and GND will be small.

Also regarding the via into the DSI lanes, you could SWAP lanes so you could avoid using vias, please check the datasheet of the processor you are using to make sure that could be swapped, but usually it could be swapped.

Thanks

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