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In the below circuit, I know the voltage at collector is 180 degree lagging.
Also easy to see that the voltage at emitter is same as input voltage and thus 0 degree lagging.

What I don't understand is how C3 and R5 change this circuit.

How are they allowing the out to vary in phase between 0 and 180 degrees?

I know when R5 = 0 the out is shorted to emitter, so phase shift is 0 degrees.
But we're "connecting" collector to emitter through C3, R5, doesn't this affect the ac behavior?

Because the emitter resistor now has two paths for ac current:

  1. From emitter
  2. From collector->C3->R5.

schematic

simulate this circuit – Schematic created using CircuitLab


My work:

If it is okay to assume collector and emitter as ideal voltage sources with values \$ V\angle 180, V\angle 0 \$ respectively. Then voltage divider of capacitor and resistor gives the phase shift: $$\phi = -\pi+2\arctan \dfrac{X_C}{R}$$

This algebra cleared up most of my original confusion, but why collector and emitter act as ideal voltage sources? somehow that extra branch to the emitter resistor is still throwing me off...

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  • \$\begingroup\$ What is the value of R1? \$\endgroup\$ Mar 3, 2022 at 19:54
  • \$\begingroup\$ @JohnBirckhead 2.2k, unity voltage gain \$\endgroup\$
    – across
    Mar 3, 2022 at 19:58

3 Answers 3

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Assumptions:

  1. You are omitting the contribution of base current, and assume that the emitter current and collector current are identical (very high Beta).

  2. You stay in the small-signal region (no distortion from saturation, and the input sine wave amplitude is small enough).

  3. Your output is open (very high impedance).

Then:

  1. The emitter voltage is always one diode drop below the base voltage. Since your base voltage is a pure sine wave, the emitter voltage is also a pure sine wave with the same amplitude.
  2. The emitter and collector are completely symmetrical; they see the same impedance.
  3. Since the emitter and collector have the same current, into the same AC impedance, the AC component if their voltages must be identical (with opposite polarity.)

Of course in real life, the currents differ by the amount of base current, so the currents are unequal.

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  • \$\begingroup\$ While this is true it does not answer the OP's question, "But why collector and emitter act as ideal voltage sources?" \$\endgroup\$ Aug 24, 2023 at 8:56
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I imagine the circuit this way: on the LHS of C3 there is a negative voltage prior to the degenerated amplifier in the first step. On RHS of C3 there is a positive voltage prior to the original input wave. The RC circuit formed by C3 and R5 can be thought as a delay circuit acting on the positive wave thru the mathematical relation t=RC. Because of the potential difference created across the capacitor prior to its negative and positive plates there is created an interference between the two waves, either a constructive interference or a destructive one. Imagine two ideal sinusoidal waves with the same amplitude and characteristics, the only difference being that one wave leads the other by 180°. Adding the two waves together equals 0 (the equivalent of destructive interference). enter image description here

This fits well the part where you say that at 0 resistance of R5 the phase shift is 0, the result of destructive interference. You can imagine the two amplitudes of the waves as two ever changing amplitudes that are equal in value but opposite in sign. It is like adding 5+-5=0 (but here we encounte the derivatives of waves which will always change but they will also always add up to 0). Constructive interference is the opposite. Two waves that are in sync with no phase shift will add up to create a bigger wave. enter image description here

The circuit translates the interference to a corresponding phase shift. 0 phase shift corresponds to destructive interference. Phase shift corresponds to constructive interference. The ciruit is resonating and responding when there is constructive interference. Via mathematics you can get the equation above that you mentioned which counts for this interference. Again, think of the RC between C3 and R5 as a delay circuit, not a power dissipating one. The RC only delays the positive wave, creating a phase shift. By changing R5 you change the time constant RC. The circuit takes the interference in the form of a phase shift. You asked this question a while ago, so it is likely that you don't have a problem with this circuit anymore, but even so I am happy with either possibility. If you want to understand better my explanation, please search on wikipedia about destructive an constructive interferance between two or more waves https://en.wikipedia.org/wiki/Wave_interference?wprov=sfla1. Have a nice day!

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  • \$\begingroup\$ I feel there are rational points in your reasoning but can't you try to say it more simply and clearly? \$\endgroup\$ Aug 24, 2023 at 8:59
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Can not be!

... but why collector and emitter act as ideal voltage sources?

When I read this, my knee-jerk reaction was that this is not true (at least for the collector output). That the transistor seen from the side of the collector was a current and not a voltage source? And if the resistance in the collector circuit changes, the voltage drop across it will also change?

Let's test it!

We can explore it using CircuitLab, first in DC mode (no AC input source, only bias as input). We can simplify the circuit by replacing the collector and emitter 2.2 k resistors with "deliberately degraded" ammeters with an internal resistance of 2.2 k. Also, let's include voltmeters in parallel to the resistors to see the voltage drop across them.

DC experiments

No collector load: The transistor Q acts as a "disturbed emitter follower". It copies its base (bias) voltage Vb2 to its emitter (across the emitter resistor Re). For this purpose, Q passes its collector current through Rc and Re to roughly adjust Ve = Vb. Thus the same current flows through Rc and Re; so VRc/VRe = Rc/Re. The two resistors separated by the transistor act as an "ideal voltage divider" with a gain of Rc/Re (< 1, =1 or > 1).

schematic

simulate this circuit – Schematic created using CircuitLab

Collector load to ground: If we connect a load RL between the collector and ground, it sinks an additional current from Rc and the voltage VRc across it increases.

schematic

simulate this circuit

We can see from the DC sweep simulation below that Q does not compensate for the RL intervention; so it does not behave as a constant voltage source.

STEP 2

Emitter load to ground: In contrast, if we connect the load RL (an intentionally worsened voltmeter with 10 k internal resistance) between the emitter and ground, it sinks an additional current from the emitter and the voltage VRe should decrease. But now Q increases its collector current thus roughly compensating the voltage drop (i.e., it behaves as an imperfect voltage source).

schematic

simulate this circuit

STEP 3

Load between the collector and emitter: If we move the lower end of the load RL from ground to the emitter, something interesting happens. The load current leaves the collector but is not lost to ground but returns back to the emitter. This "helps" the transistor by forcing it to reduce its collector current. As a result, the collector voltage rises. Thus, the collector output approaches in behavior to a voltage source.

schematic

simulate this circuit

We can see the result of this clever trick in the DC sweep simulation below - at RL > 4 k the graph is almost horizontal.

STEP 4

AC experiments

No collector load:

schematic

simulate this circuit

Collector load to ground:

STEP 5

schematic

simulate this circuit

STEP 6

Load between the collector and emitter:

schematic

simulate this circuit

STEP 7

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