I am using a NUCLEO-L432KC board DATASHEET I am trying to configure the ADC conversion with a 10k potentiometer However the ADC seems to give a wrong results
I set the pot to output 5v (asserted with a multimeter) and used the result to control PWM duty cylcle on an LED However the glowing of the led seemed constant (no changes in the duty cycle by varying the pot)
The gdb output of the ADC_DR register shows the result of the ADC conversion changes to a wrong value immediately after reading it and stays that way
(gdb) x/d &ADC_DR
0x50040040: 4095
(gdb) x/d &ADC_DR
0x50040040: 1703
(gdb)
The 4095 is the intended result for me as the multimeter shows 5v however the result goes back to arbitarly value under 2k without no instructions executed in between tried to raise the Sampling time to 24.5 clock cycles with no luck
The ADC_init function is as shown:
main:
bl clockInit80
bl TIM2_PWM_Init
bl ADC_Init
1:
ldr r1, =ADC_CR
ldr r0, [r1]
orr r0, #(1 << 2) @ADCSTART = 1
str r0, [r1]
@wait for the conversion to complete
mov r0, #30
delay:
subs r0, #1
bne delay
@read ADC_DR
ldr r1, =ADC_DR
ldr r0, [r1]
ldr r2, =5000
mul r0, r2
ldr r2, =4096
sdiv r0, r2
@store the result in TIM2_CCR1
ldr r1, =TIM2_CCR1
str r0, [r1]
ldr r1, =TIM2_EGR
ldr r0, [r1]
orr r0, #(1 << 0)
str r0, [r1]
b 1b
ADC_Init:
@Select clock source for the ADC (Mandatory) else no clock
ldr r1, =RCC_CCIPR
ldr r0, [r1]
orr r0, #(3 << 28) @ADCSEL Bits [29:28]
str r0, [r1]
@Enable clock for ADC
ldr r1, =RCC_AHB2ENR
ldr r0, [r1]
orr r0, #(1 << 13) @ADCEN Bit 13
str r0, [r1]
@Disable deep down power mode Bit 29
ldr r1, =ADC_CR
ldr r0, [r1]
mvn r2, #(1 << 29)
and r0, r2
str r0, [r1]
@Enable the ADC voltage regulator ADVREGEN
ldr r1, =ADC_CR
ldr r0, [r1]
orr r0, #(1 << 28)
str r0, [r1]
@ADC voltage regulator average wake up time is 20us wait for 50us
@waitStart
ldr r0, =4000
1:
subs r0, #1
bne 1b
@waitEnd
@set the number of ADC conversion to be single conversion
ldr r1, =ADC_SQR1
ldr r0, [r1]
orr r0, #(1 << 0) @L (sequence legnth) Bits [3:0]
str r0, [r1]
@set the first (and only channel to be channel 5 (ADC_IN5 = PA0)
ldr r1, =ADC_SQR1
ldr r0, [r1]
orr r0, #(5 << 6) @SQ1[10:6]
str r0, [r1]
@set channel 5 adc sampling time to be 24.5 clock cycles
ldr r1, =ADC_SMPR1
ldr r0, [r1]
orr r0, #(3 << 15)
str r0, [r1]
@Enable ADC first clear the ADRDY bit
ldr r1, =ADC_ISR
ldr r0, [r1]
orr r0, #(1 << 0)
str r0, [r1]
@Set the ADEN bit in ADC_CR
ldr r1, =ADC_CR
ldr r0, [r1]
orr r0, #(1 << 0)
str r0, [r1]
@wait for ADRDY bit to be set
1:
ldr r1, =ADC_ISR
ldr r0, [r1]
tst r0, #(1 << 0)
beq 1b
@return
bx lr
EDIT1: The PA0 is connected directly to the 5v output from the 10k pot (PA0 is 5v tolerant as indicated in the datasheet)
AGAIN it actually shows the correct value for the conversion for a sec but it changes immediately to a wrong one so I don't think the problem has anything to do with the connection and it's varying by hunderds of digits as shown above
EDIT2: The 5V is changed to 3.3V as suggested and the ADC is asserted to be working fine using cubeMX and HAL code (No damage from the 5V the ADC_DR in the HAL code is constant with the correct value) The clock is configured to be the system clock at 80Mhz I suspect the problem is in my initialization code but I am already following the reference manual init sequence maybe there's some detail I am missing
Connection Schematic