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I am working on a PCB with a Toshiba motor driver chip, TB9051FTG.

https://www.digikey.com/en/products/detail/toshiba-semiconductor-and-storage/TB9051FTG-EL/10123940

The datasheet mentions the requirement of a circuit to protect the power source enter image description here

I have implemented it with this circuit enter image description here

I have this power circuit that is meant to serve as a power source protector as mentioned

The VM is the power input VBAT, 1, 2,3 for the chip

enter image description here

I have a couple of questions that deal with trace width.

  1. How wide should the trace between VIN and power transistor pin 2 be?
  2. How wide should the VM trace be?

Early research would suggest about 368 mils. enter image description here

I have been looking at this example breakout board for reference, https://www.pololu.com/product/2520 and it does not seem like the power connections are that wide, especially between the diode and VBAT inputs of the chip.

UPDATE

I have taken a look at the breakout board PCB and done some current probing on that board. The current between VIN and the diode and the current betwen the diode output and VBAT on the chips looks to be 11A-12A at pretty much all times.

I also looked at how they did the power traces. It looks like they just sectioned off large part of the board to conduct the power current. Could someone verify that my assumptions about the division of copper for power traces in the image of the breakout board below makes sense?

Yellow - VIN

Purple - VM

Red - TB9051FTG #1 OUT/OUT1 or OUT/OUT2

Blue - TB9051FTG #1 OUT/OUT1 or OUT/OUT2 (opposite output of red)

Green - TB9051FTG #2 OUT/OUT1 or OUT/OUT2

Cyan - TB9051FTG #2 OUT/OUT1 or OUT/OUT2 (opposite output of green)

enter image description here

If this is the case, then probably those division of copper are about as wide as whatever trace I would have considered making (around 200 mils I'm guessing.)

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  • \$\begingroup\$ External layer only says 142 mil. Also 20°C temperature rise is probably acceptable. \$\endgroup\$ Mar 5, 2022 at 22:16
  • \$\begingroup\$ Switched to 20 degree temp rise and on external layer that is 93 mil, which as I lay down the trace seems much more reasonable \$\endgroup\$
    – Jack Frye
    Mar 6, 2022 at 3:47
  • \$\begingroup\$ Also from what I'm reading 1oz/ft^2 is more common than 2oz/ft^2 for thickness. If I make that switch, I end up at 186mil for external layers, which again seems pretty big. Do PCB tools give you that ability to change thickness on trace by trace basis? \$\endgroup\$
    – Jack Frye
    Mar 6, 2022 at 14:51
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    \$\begingroup\$ Copper thickness on one pcb layer will always be the same because the base material is a sheet of copper and some of the copper is etched away to leave the pcb traces behind. Maybe you can reconsider the 10A current as well. If 10A is only a peak current for a few seconds and continuous current is only ~5A, you can get away with smaller power traces. Use the space that is available. Short sections with less width will be OK if it gets wider again nearby. \$\endgroup\$ Mar 6, 2022 at 15:17
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    \$\begingroup\$ That makes sense. I assume that property is what is taken advantage of when you have a QFN package (like this chip) and the pins are closer together than the theoretical width of the trace required? \$\endgroup\$
    – Jack Frye
    Mar 6, 2022 at 15:22

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