# Series RLC circuit - Phase difference between voltages across inductor and resistor is not exactly 180, why?

In phasor analysis we put inductor voltage along positive $$\j\$$ axis and capacitor voltage along negative $$\j\$$.
So these two voltages are exactly $$\180\$$ degrees apart.

But in simulation below, the two voltages are not meeting on $$\t\$$ axis. Why?

simulate this circuit – Schematic created using CircuitLab

• They look 180 degrees out of phase to me, just with a DC offset. Mar 6, 2022 at 13:08
• Oh right! Looks capacitor has some transient voltage at t=0... Mar 6, 2022 at 13:10
• Your title is in error. Mar 6, 2022 at 13:30
• @Andyaka I see now... got mixed up DC offset with phase. I should have more faith in math haha Mar 6, 2022 at 13:34

Vc has a DC offset , otherwise it appears to be in sync with resonance after 10T for T=RC=100us, it should be discharged from any initial condition within reason.

I never use Circuit Lab.

However the initial voltage on Vc is create by sin 0 deg and not an initial Vdc condition. Starting with sin 90 deg will result in 0 V offset.

## trivia

Remember this fact of initial conditions for sin voltage thru an LC circuit

When current is interrupted, in order to prevent the initial condition of remanence and possible saturation of the core with a very loud core hum, companies like ABB make smart reclosure power switches to reclose the grid at the same voltage phase as when it was interrupted . The transformer current will decay L/R=T but not after experiencing huge winding stresses on the order of tons from transient core saturation.

Note the two simulations for initial voltage phase of 0 then 90 deg, how it creates initial voltages for L and C differently and Vc starts with a Vp DC offset voltage with Sin 0.

My Falstad Simulation. Right clock source to change phase then press reset and stop whenever.

I just noticed my error in placing the Cap from bottom to top so my voltage was displayed inverted. So I selected Cap, the "swap ends" and replotted

• Thanks! I just simulated again. After ~1s, the average voltage on capacitor is indeed going to 0. Then circuitlab must be assuming some initial voltage on capacitor at t=0. Wish there is some way to set initial conditions in circuitlab... Mar 6, 2022 at 13:12
• Like Falstad's , there must be an option Mar 6, 2022 at 13:14
• @across There's no "ghostly" initial voltage, they're zero but what you see is the effect of a normal RLC transient response. You just have to wait long enough for these to decay. Even 1 ms is enough. Mar 6, 2022 at 13:19
• @aconcernedcitizen haha ok you mean at t=0, the voltage on capacitor is 0, but the capacitor starts charging up in positive direction(sin(wt) input). So there is asymmetry initially and this decays over time. Is my understanding accurate? Mar 6, 2022 at 13:22
• The remanence charge in large power transformers has a long enough time constant that if you don't power up in the same phase as your left off, it can damage windings from huge current forces if the core saturates from voltage and not load current. When cores saturated L goes towards 0 and all that is left is DCR. Otherwise in order to quench the grid energy at the zero-crossing during a breaker fault condition is quenching a possible large energy arc. So > 100 MVA transformers can be quite expensive built like a tank. Mar 6, 2022 at 14:44