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I have this code for Knight Lights in VHDL and I have few questions.

  1. Why in shift_reg <= shift_reg(6 downto 0) & '0'; if( shift_reg(6) = '1') then the 6th bit is set to '1' and not the 7th bit which is the last ?

  2. Same question with shift_reg <= '0' & shift_reg(7 downto 1); if (shift_reg(1) = '1') then why 1st bit is set to '1' and not bit zero set to '1' ?

The design works fine, but I do not understand these parts. Thanks!

use IEEE.STD_LOGIC_1164.ALL;

entity Basys3Demo is
    port ( 
              clk : in STD_LOGIC;
              led : out  STD_LOGIC_VECTOR (7 downto 0)
           );
end Basys3Demo;

architecture Behavioral of Basys3Demo is

signal shift_reg : std_logic_vector (7 downto 0) := "00000001";
signal polarity  : std_logic := '1';
signal count : integer range 0 to 50000000;

begin

process (clk)
begin

    if (clk'event and clk = '1') then
        if (count < 50000000) then
            count <= count +1;
            else
            count <= 0;
            
        if (polarity = '1') then
            shift_reg <= shift_reg(6 downto 0) & '0';
        if( shift_reg(6) = '1') then
             polarity <= '0';
        end if;
       else
           shift_reg <= '0' & shift_reg(7 downto 1);
           if (shift_reg(1) = '1') then
             polarity <= '1';
          end if;
         end if;
        end if;
       end if;

    end process;
    
    led <= shift_reg;
end Behavioral;```
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  • 1
    \$\begingroup\$ "The program works fine"... Hmm it's not a program, it's a hardware. \$\endgroup\$
    – Mitu Raj
    Mar 7, 2022 at 17:20
  • 1
    \$\begingroup\$ A warm welcome to the site. As @MituRaj correctly pointed out, you don't have a 'program'. You have a 'design'. I hope you're OK with me changing that term in your answer. A program runs on a CPU, whereas VHDL is a descriptor language for describing digital logic circuits. An HDL is much more of a glorified netlist than anything else. When synthesized, it produces a circuit. May sound like small detail but it's actually paramount to designing solid, reliable circuits with VHDL. Dreadful VHDL is knocked out by people trying to write programs in it. Good to avoid that pitfall and pain it brings. \$\endgroup\$
    – TonyM
    Mar 7, 2022 at 19:39

1 Answer 1

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In VHDL, when you write some_reg <= some_value, some_reg only takes on some_value after the clock cycle has completed. If some_value depends on some_reg, then throughout your block the old value of some_reg is used.

So when you test for shift_reg(6) = '1' you are predicting that shift_reg(7) will be 1 on the next clock cycle.

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  • \$\begingroup\$ What if I wanted 2 LEDs to move and not one ? Should I just change the signal shift_reg : std_logic_vector (7 downto 0) := "00000001"; to signal shift_reg : std_logic_vector (7 downto 0) := "00000011"; \$\endgroup\$
    – Matas
    Mar 8, 2022 at 21:47

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