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The STWD100 is a watchdog timer, if a pulse from a microprocessor isn't received in X amount of time, it pulls it's output low. This is useful to detect if a processor has experienced an upset (independent of the processor itself). This is the timing diagram of what I want the STWD100 to do:

enter image description here Source: https://www.st.com/content/ccc/resource/technical/document/datasheet/06/6a/b3/83/9a/c7/4f/22/CD00176077.pdf/files/CD00176077.pdf/jcr:content/translations/en.CD00176077.pdf

I want it to pull the output low if WDI changes and I would like it to stay low There is no way I have found to do this with the STWD100PY chip. Apparently normal triggering is not really an option and timeout without retrigger is the only option.

enter image description here Source: https://www.st.com/content/ccc/resource/technical/document/datasheet/06/6a/b3/83/9a/c7/4f/22/CD00176077.pdf/files/CD00176077.pdf/jcr:content/translations/en.CD00176077.pdf

I've checked a few other circuits and cannot find a good simple way to implement this functionality. Anybody know a good way to have a timer watchdog circuit in a small footprint that goes low and stays low?

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    \$\begingroup\$ SO you want to latch a Timeout rather than perform a reset? That's easy with a retriggerable timer and latch \$\endgroup\$ Commented Mar 8, 2022 at 0:37

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schematic

simulate this circuit – Schematic created using CircuitLab

Not sure if this satisfied your design spec and timing diagram

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The TPS3431 goes low and stays low

enter image description here

https://www.ti.com/lit/ds/symlink/tps3431.pdf?ts=1717075046403

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