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There is a function called __disable_irq(); in ARM microcontrollers CMSIS library and does something which I don't understand.

It is defined as:

__STATIC_FORCEINLINE void __disable_irq(void)
{
  __ASM volatile ("cpsid i" : : : "memory");
}

It is always under Error_Handler fucntion if you use HAL library:

  * @brief  This function is executed in case of error occurrence.
  * @retval None
  */
void Error_Handler(void)
{
  /* USER CODE BEGIN Error_Handler_Debug */
  /* User can add his own implementation to report the HAL error return state */
  __disable_irq();
  while (1)
  {
  }
  /* USER CODE END Error_Handler_Debug */
}

For example when initializing uart:

  /* USER CODE END USART2_Init 1 */
  huart2.Instance = USART2;
  huart2.Init.BaudRate = 38400;
  huart2.Init.WordLength = UART_WORDLENGTH_8B;
  huart2.Init.StopBits = UART_STOPBITS_1;
  huart2.Init.Parity = UART_PARITY_NONE;
  huart2.Init.Mode = UART_MODE_TX_RX;
  huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE;
  huart2.Init.OverSampling = UART_OVERSAMPLING_16;
  huart2.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
  huart2.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
  if (HAL_UART_Init(&huart2) != HAL_OK)
  {
    Error_Handler();
  }
  /* USER CODE BEGIN USART2_Init 2 */

What really happens here hardware wise if HAL_OK returns false? Does the microcontroller reset? What does __disable_irq() do?

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2
  • \$\begingroup\$ What is the ARM microcontroller you’re referring to? Be it Cortex M0.3.4 or 7 may affect the answer. \$\endgroup\$
    – Kartman
    Commented Mar 8, 2022 at 22:16
  • \$\begingroup\$ M4 at the moment \$\endgroup\$
    – GNZ
    Commented Mar 9, 2022 at 8:33

1 Answer 1

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__disable_irq() disables all interrupts, with the exception of a few non-maskable ones, preventing interrupt handlers from running as a result of stimuli such as timers, pin changes, incoming I/O, etc.

When this is followed with a while(1) {}, this intentionally locks up the processor until it is reset. This is preferable to having a program that's still running or handling interrupts, in an unknown state, after an unrecoverable error.

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2
  • \$\begingroup\$ I don't think that the Cortex-M has FIQ interrupts. \$\endgroup\$ Commented Mar 8, 2022 at 19:18
  • \$\begingroup\$ @ElliotAlderson Thanks, removed that section \$\endgroup\$
    – nanofarad
    Commented Mar 8, 2022 at 19:21

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