PMOS/NMOS current direction and digital logic

What happens when the PMOS source is connected to negative Vcc (-Vcc).
What I understand is that when the gate voltage is <=0 then the drain-source is connected. Normally I would expect current to flow from source to drain but since the source is connected to -Vcc. Is this correct? Also, how can I think the behaviour for of multiple MOSFET connected together.
ie I have the PMOS as described above and at the drain another PMOS is connected. Assumming that the above statement is correct and current flows from drain to source does that mean that the second PMOS will be OFF?

I hope this is not very confusing...I am new to this.

• In PMOS, Vgs must be less than zero to turn on the channel between drain and source. Also, the "normal" case for PMOS is with Vs > Vd. Normal discrete PMOS has a parasitic diode from drain to source. So if Vd > Vs, current will flow through the parasitic diode even if Vgs >= 0. Mar 10, 2022 at 22:01
• Why does Vgs need to be less than zero? I thought as long as Vg is less than zero then the PMOS is ON. Assuming the parasitic diode is forward bias from as current flows from drain to source, then how does current if Vd>Vs when no channel forms since Vgs >=0? Mar 10, 2022 at 22:23
• No, your thinking was not correct. For a PMOS enhancement transistor we require that $V_{GS} < 0$ in order for the transistor to conduct significant current. Perhaps you should draw a schematic, as your word descriptions are unclear. Mar 11, 2022 at 2:47

Here is a typical PMOS circuit. I drew in the body diode so you can see which way it points. Note how the body diode in NMOS points in the opposite direction from the body diode in PMOS.

This circuit works as follows: When VCC is present, M2 turns ON and pulls down the gate of M1, which then turns M1 on.

When VCC is not present, the gate of M2 is low, so M2 is off, which means that M1's gate will be high (if the external signal is high) and M1 will be off. R1 ensures that M1 will remain off unless M2 is on.

MOSFET's are controlled by the gate-to-source voltage. For NMOS, driving Vgs high turns it on. For PMOS, driving Vgs low (less than zero) turns it on.

I should probably mention that I am talking about enhancement mode MOSFET's, which are the most common ones. I just don't want to talk about depletion mode MOSFET's at all because it might be confusing.

In this circuit, if the drain of M1 is higher than the source, then the body diode will become forward biased and will conduct. M1 cannot block current from flowing into the external signal wire. It just acts like a diode in that direction.

simulate this circuit – Schematic created using CircuitLab