The datasheet for Mornsun K7805MT-500R4 DC-DC module has the usual required capacitors in typical application circuit:

typical application

And just as pretty much any other datasheet they provide additional schematics for EMC compliance on the input:

EMI filter

However, unlike all other datasheets I've seen before, they seem to use input bypass capacitor as part of the filter on Vin side of the inductor, leaving much smaller capacitor on the converter side. More than that, it looks like they do not use C3 in some cases at all, leaving DC-DC without bypass. For comparison, here is the CUI VX78-500 datasheet, which has both bypass and filter capacitors in addition to the EMC components, as it is usually done.

typical EMI filter

Note, that although the two circuits look exactly the same, they are not! In the Mornsun case 10uF C1 bypass becomes C2 part of the filter on the Vin side of the input. Much smaller 0.47uF C3 is additional part of the filter, and it is not even used for 5V output. In the CUI (and hundreds if not thousands other converters) case, 10uF C1 bypass remains where it was, while 4.7uF C5 is added as part of the LC filter. In fact, many datasheets have several capacitors in parallel between inductor and converter, large one for bypassing and small (in 0.01-0.1uF range) for CLC filter.


Is this an error in the datasheet or one can in some cases get by with such an unusual arrangement? Somehow I don't think the capacitor can work as bypass if it is separated from the load by inductor.


2 Answers 2


You'll need to evaluate any such filter circuits anyway, so you may as well do so now and answer your own question. It's not a good idea to trust such application circuits unquestioningly. See how the regulator performs in terms of noise, and line and load regulation in response to input voltage and load current transients. Errors in datasheets are commonplace for parts that don't have a long legacy, so I'd not be surprised.


Is this an error in the datasheet?

Is is an error in your assumption to presume you know better than assume this is a mistake.


  • Load voltage % regulation error is basically the ratio of source to total Load_source impedance.
    Load Reg. Error= Rs/(Rs+Rload)100%

  • This is easily proven by looking at Zout, Zload and DCDC converter Load regulation spec. Then using the Bode plot for the same step load test, and phase response must disturb the loop filter. Here only the switch frequency is known. (2 MHz)

  • If you eliminate all output voltage ripple, you have lost all the sensitivity to load shifts. So some ripple is essential but improved by raising switch frequency.

  • Some loads are reactive and this 5 V, 0.5 A supply can tolerate up 680 uF load for energy storage and stabilization.

  • The efficiency drops with input voltage as the load effectively is 10 Ohms raises the Q but by choosing an optimum, RdsOn, DCR, ESR they have reported the optical LC components using ceramic for the non-polar.

Input filters need to perform these major tasks;

  1. Attenuate current source ripple noise egress
  2. Attenuate output voltage ripple egress from supply sensitivity (PSRR)
  3. Stabilize input voltage during a step voltage load .
  4. Minimize excess stored energy during shunt mode to avoid overshoot from inertia of current during shunt-turn-off
  5. Tradeoff loss in loop filter phase margin from no-load to full-load for ripple rejection.

Adding the missing capacitor can reduce the phase margin for the voltage/current impedance ratio and phase margin over a wide range in input voltages and output loads.


  • This is not a perfect representation of noise transfer function as it neglects the spectrum noise generated by the 2 MHz switch and spectrum of step loads over range, ratio and direction of load shifts.

  • if you use efficiency to represent the average DCDC convert series resistance and the load resistance of 5 V / 0.5 A = 10 Ohms minimum for the average, the step load can could be capacitive with a much lower ESR. This affects the steady-state ripple and step load noise and is used in simulation.

The assumption is that the DC-DC converter will have a feedback BW what is between 15 kHz and 5% of the switching frequency. So the phase shift is shown at 15 kHz with the C3 included and C3 removed. The result is a 80 deg phase shift reduction that benefits the phase margin of the DC-DC loop filter.

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The conclusions

You must define goals then model all the variables then design and test the sensitivity to phase margin and noise for every variable in order to meet the design specs published.

The mfg has obviously done a lot of R&D to recommend these values. You may find differences from supply components and layout so following their directions is key unless you can demonstrate you have more experience than they and found a way to obtain better performance for your application and layout to meet the same specs.

Essentially eliminating the C3 just adds the LDM2 to the internal series input L.


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