See explanatory image.

If the power net (3.3 V) for my microcontroller runs out of power (detected with brown out detection) I make the gate to my P-MOSFET go high and this "disconnects" the 3.3 Vin (that is rapidly losing its voltage level now) and "traps" the remaining power in the "VCC-net" with the capacitor.

This should allow the microcontroller to shut down in a controlled manner (saving all necessary data before running out of power).

So... why is this not working?

I can see that the software is doing its part: the gate-pin is going high directly when the 3.3 Vin-net is going under 3.1 V, so it seems to be a hardware issue.

Is it because I don´t have enough capacitance in the capacitor to keep the VCC voltage high long enough?

Because as I understand it the general rule is like this for a P-MOSFET switch:

gate voltage (0 V) - source voltage (3.3 V) = -3.3 V. This is more negative than -0.9 V (gate threshold) so the switch is "ON".

gate voltage (3.3 V) - source voltage (3.3 V) = 0 V. This is less negative than -0.9 V (gate threshold) so the switch is "OFF"

So in the case of power loss it should be something like this:

gate voltage (3.3 V) - source voltage (0 V) = +3.3 V. This is less negative than -0.9 V (gate threshold) so the switch is "OFF" (gate voltage staying at 3.3 V because of the capacitor).

Or is there some other reason why this is not working? Because the VCC net is going down as fast as the 3.3 V net... Is the cap not holding the net up long enough maybe?

I also noticed the voltage on the drain side (closest to the microcontroller) is lower than the source side.

The drain side is maybe 2.6 or 2.8 V or so when the source side is 3.3 V. How come? Since Rds(on) is only 50 mΩ? It should be 3.3 V on both sides? or?...

What am I missing here?


Microcontroller: ATSAMD21E18A-AUT

enter image description here


1 Answer 1


The FET is in backwards. Look at the schematic symbol, and you will see a diode from the drain to the source. When the 3.3 V input gets low enough, that diode is forward-biased, and conducts current from the holdup cap (reference designators - !).

Reversing the drain and source solves this issue, but might cause a different one. Now the full 3.3 V source will bypass the FET and power the circuit through the diode even if the FET is off. This normally is not a problem, and allows the circuit to power up no matter the power-off condition of PA07.

If you measure the continuous current the circuit draws, you can calculate the capacitor size for any hold-up time period.


The current drawn by the circuit might be depleting the capacitor's charge as fast or faster than the 3.3 V source is decreasing. Without knowing the current the capacitor has to supply, all is guesswork.

Here is a guess: Since we have no information, let's assume that the circuit can operate down to a power supply voltage of 2.3 V. Let's also assume that the operating current is 1 mA.

E x C = I x t

Capacitor voltage decrease time the capacitor value equals the discharge current times the time it takes to discharge E volts.

E = 3.3 - 2.3 = 1.0 V C = 220 uF = 0.00022 F I - 1.0 mA = 0.001 A

Rearrange and calculate - - - t = 0.22 seconds.

So with the schematic you posted, the holdup time is less than 1/4 of a second. It might be that the circuit is behaving normally.

  • \$\begingroup\$ Ah the diode. I did not think of that one....*facepalm*... So reversing the drain and source pins just like that work? nothing strange happens? it just....work? it is the same thing but with just the dioden turning the other way? sorry for stupid question. But I have no idea.. \$\endgroup\$
    – mannen
    Commented Mar 13, 2022 at 23:52
  • \$\begingroup\$ sorry. It is wrong in the paint-image. It is actually as you suggested. the diode is the other way around from how it is in this image. So must be some other issue... \$\endgroup\$
    – mannen
    Commented Mar 14, 2022 at 0:28
  • \$\begingroup\$ See the update. \$\endgroup\$
    – AnalogKid
    Commented Mar 14, 2022 at 1:25

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